Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Chiaki Takubo"'
Autor:
Hideki Shibata, Hideto Furuyama, Hiroshi Hamasaki, Hideo Numata, Hiroshi Uemura, Chiaki Takubo
Publikováno v:
2008 58th Electronic Components and Technology Conference.
A high-performance 160 Gbps (=20 GB/s) optical semiconductor module using an optoelectronic (OE) ferrule with the ultra-compact size of 4.4 times 4.5 times 1.0 mm3 was developed for the first time in the world. The ferrule is used as the interface of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebccf530e3a59d10fb6bfd37b86c61bd
https://doi.org/10.1109/ectc.2008.4550247
https://doi.org/10.1109/ectc.2008.4550247
Publikováno v:
33rd European Conference and Exhibition on Optical Communication - ECOC 2007.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::251d2d58e927c6350b28302d3cb06505
https://doi.org/10.1049/ic:20070438
https://doi.org/10.1049/ic:20070438
Autor:
Hiroshi Hamasaki, Mitsuaki Tamura, Hideo Numata, Kenichiro Ohtsuka, Chiaki Takubo, Wataru Sakurai, Hideto Furuyama, Kazuhito Saito
Publikováno v:
2006 European Conference on Optical Communications.
We developed an optoelectronic ferrule using hoop injection molding. By mounting a vertical cavity surface emitting laser (VCSEL) (or photo diode (PD)) directly on the end-face of the ferrule, an extremely simple and cost-effective optical interconne
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cffc975018bdab7d1415734d2e3c46e
https://doi.org/10.1109/ecoc.2006.4801246
https://doi.org/10.1109/ecoc.2006.4801246
Publikováno v:
56th Electronic Components and Technology Conference 2006.
A novel optoelectronic LSI package using a post-reflow optical-interface stacking technique (POST), which enables high speed operation at more than 10 Gbps/ch on the standard FR-4 PWB was proposed. The POST LSI package includes an interposer and an o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::833df6211e7f96fc2739bf1635f3a4ce
https://doi.org/10.1109/ectc.2006.1645662
https://doi.org/10.1109/ectc.2006.1645662
Autor:
Katsumi Hisano, Kenji Hirohata, Hideo Aoki, Takashi Kawakami, Michael Pecht, Chiaki Takubo, Minoru Mukai
Publikováno v:
Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology.
In order to improve electronics packaging design, it is important to evaluate the cooling performance and reliability of the electronics packaging structure of a product. To that end, it is necessary to predict the temperature, deformation, and stres
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::70d2c643b0817679f757fb21728c4e03
https://doi.org/10.1115/imece2006-13800
https://doi.org/10.1115/imece2006-13800
Autor:
Wataru Sakurai, Hiroshi Hamasaki, Kazuhito Saito, Mitsuaki Tamura, Kenichiro Ohtsuka, Chiaki Takubo, Hideto Furuyama, Hideo Numata
Publikováno v:
2006 8th Electronics Packaging Technology Conference.
Attention has turned in recent years to optical interconnection as the most cost-effective solution to the problem of I/O bottlenecks in the wiring of conventional FR4 printed wiring boards. In this paper we propose a new configuration for the key el
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::194024a7083e1dfb5cb467e5d3f1d631
https://doi.org/10.1109/eptc.2006.342744
https://doi.org/10.1109/eptc.2006.342744
Publikováno v:
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium.
Chip Scale Package (CSP) has been developed by applying the flip chip technology with the eutectic Sn/Pb solder bumps. The package size is only 1 mm larger than the chip size. The eutectic solder has advantages such as a good wettability to the elect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eb52d55709e7d148122c40ac3f9d145
https://doi.org/10.1109/iemt.1996.559794
https://doi.org/10.1109/iemt.1996.559794
Autor:
Soichi Honma, Takahito Nakazawa, Hirokazu Ezawa, Yoichi Hiruta, Hideo Aoki, K. Doi, Chiaki Takubo, Masahiro Miyata
Publikováno v:
1997 Proceedings 47th Electronic Components and Technology Conference.
Eutectic solder flip chip fabrication technology, through bumping to assembly process, has been developed. In bumping process, electroplating method and thick photo resist process could form eutectic solder bumps whose uniformity of height are less t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d56c5d35743212168d28adc0ff069573
https://doi.org/10.1109/ectc.1997.606188
https://doi.org/10.1109/ectc.1997.606188
Publikováno v:
1995 Proceedings. 45th Electronic Components and Technology Conference.
A 50 /spl mu/m pitch TAB has been developed by applying newly developed TAB tape and inner lead bonding technology. A new electrodeposited Cu foil which has a high tensile strength and 18 /spl mu/m thickness was adopted as the lead material. Sn plati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ded4d0054b949b29bf2c6773d1c961c
https://doi.org/10.1109/ectc.1995.517787
https://doi.org/10.1109/ectc.1995.517787
Publikováno v:
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
The achievement of rapid advances in integration density and performance of LSI devices is predicated on increasing the total number of Input/Output (I/O) and Power/Ground (P/G) terminals, which, in turn, leads to shrinking design rule of wiring and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93b7d2ed2bfd8154f01573d5505f9155
https://doi.org/10.1109/ectc.2000.853403
https://doi.org/10.1109/ectc.2000.853403