Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Chia-Shiung Tsai"'
Autor:
Yuan-Chih Hsieh, Lan-Lin Chao, Xin-Hua Huang, David Huang, Ping-Yin Liu, Chun-Wen Cheng, Cindy Colinge, Chia-Shiung Tsai
Publikováno v:
ECS Transactions. 50:151-158
The aluminum-germanium (Al-Ge) eutectic system was studied for the optimization of bonding parameters for hermetic sealing applications. The parameters that were varied included the ratio of aluminum to germanium, bonding temperature, force, and time
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::65be100f413bd5e362e8fb9af541b0a4
https://doi.org/10.1149/05007.0151ecst
https://doi.org/10.1149/05007.0151ecst
Autor:
K.-Y. Roy Wong, Chen Po-Chih, C. B. Wu, Ching-Ray Chen, C. W. Hsiung, Ming-Huei Lin, F. J. Yang, Liao Yan-Jie, M. W. Tsai, Yani Lai, Chiu Hsien-Kuang, Tom Tsai, Man-Ho Kwan, Sheng-Da Liu, Burn Jeng Lin, Chang Yu-Chi, Jan-Wen You, Alex Kalnitsky, Chen-Shien Chen, M.-H. Chang, J. L. Yu, L. Y. Tsai, Yu-Syuan Lin, P.-C. Liu, Ru-Yi Su, Fu-Wei Yao, H. C. Tuan, L. C. Chen, Haw-Yun Wu, K.-L. Chiu, Chia-Shiung Tsai, Chung-Yi Yu, S.-P. Wang, G. P. Lansbergen, Chiang Chen-Hao
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Bot
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7faa0d215059670d3d4fc905d6e081b
https://doi.org/10.1109/iedm.2015.7409663
https://doi.org/10.1109/iedm.2015.7409663
Autor:
H.C. Chu, Chia-Shiung Tsai, S.W. Huang, Hsien-Hsin Lin, W. S. Liao, Chung-Hao Tsai, S.P. Jeng, Doug C. H. Yu, C.Y. Pai, C.H. Chang, H.P. Hu, W.C. Chiang, Shang-Yun Hou, T.H. Liu
Publikováno v:
2014 IEEE International Electron Devices Meeting.
A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6013d9e3d3041100d0cc1b8d304f95ad
https://doi.org/10.1109/iedm.2014.7047119
https://doi.org/10.1109/iedm.2014.7047119
Autor:
Chih-Hsin Yu, Chib-Yang Pai, Chi-San Wu, Chia-Shiung Tsai, Yeur-Luen Tu, Liou Yuan-Hung, Min-Hwa Chi, Yu-Shen Chen
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 15:478-485
In this paper, the mechanism, inspection, and inline monitor of plasma charging defects found in an active area (AA) corner and edge using a poly-buffer (PB) STI process is reported. These defects are formed by the arcing (or discharging) through wea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebaa60b40712d64a4c5d227922de766c
https://doi.org/10.1109/tsm.2002.804893
https://doi.org/10.1109/tsm.2002.804893
Autor:
W.P. Mo, S. Takahashi, R.J. Lin, Kuo-Ching Huang, Gene. Hung, C.C. Chuang, Jhy-Jyi Sze, S.Y. Chen, F.J. Shiu, R.L. Lee, Jeng-Shyan Lin, Chung Wang, S. G. Wuu, W.I. Hsu, Chia-Shiung Tsai, Yeur-Luen Tu, D.N. Yaung, H.Y. Cheng, S.J. Tsai, T.H. Hsu, W.H. Wu, Y.P. Chao, S.T. Tsai, Wen-De Wang, Jen-Cheng Liu, Ta-Wei Wang, Chi-Chuan Wang
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5143c8683d3a586b5263ebe5180e7cd
https://doi.org/10.1109/vlsit.2014.6894429
https://doi.org/10.1109/vlsit.2014.6894429
Autor:
C. W. Hsiung, Chia-Shiung Tsai, C. L. Tsai, J. L. Yu, Chou Chien-Chih, Chiu Hsien-Kuang, Ping Chen Chen, King-Yuen Wong, F. J. Yang, H. C. Tuan, C. J. Yu, Sheng-Da Liu, Fu-Wei Yao, Chung-Hao Tsai, Yu-Syuan Lin, Ru-Yi Su, Xiaomeng Chen, Alex Kalnitsky, G. P. Lansbergen
Publikováno v:
2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD).
In this paper, the reliable SiN x /AlGaN/GaN MISHEMTs on silicon substrate with improved trap-related characteristics have been well demonstrated. The devices with our proposed treatment method showed less deep-level traps and more Si surface donors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d01b1c02f3be2ff85e55ca77c2e4bd9b
https://doi.org/10.1109/ispsd.2014.6856034
https://doi.org/10.1109/ispsd.2014.6856034
Autor:
Yu-Syuan Lin, Alex Kalnitsky, Ru-Yi Su, C. W. Hsiung, P.-C. Liu, Ming-Huei Lin, Chiu Hsien-Kuang, F. J. Yang, H. C. Tuan, King-Yuen Wong, S. D. Liu, J. L. Yu, Fu-Wei Yao, C. J. Yu, Xiaomeng Chen, C. L. Tsai, Yani Lai, Chia-Shiung Tsai, Ching-Ray Chen, Chen Po-Chih, G. P. Lansbergen, Chung-Yi Yu, Chiang Chen-Hao
Publikováno v:
2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD).
CMOS-compatible GaN-on-silicon technology with excellent D-mode MISHFET performance is realized. A low specific contact resistance R c (0.35 Ω-mm) is achieved by Au-free process. MIS-HFET with a gate-drain distance (L GD ) of 15 μm exhibits a large
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15f0b75d4642c065a0ced749472125e9
https://doi.org/10.1109/ispsd.2014.6855974
https://doi.org/10.1109/ispsd.2014.6855974
Autor:
Chung S. Wang, Yeur-Luen Tu, Hung-Cheng Sung, Wen-Ting Chu, Yung-Tao Lin, Yu-Hsiung Wang, Hao-Hsiung Lin, Chia-Ta Hsieh, Chia-Shiung Tsai
Publikováno v:
IEEE Electron Device Letters. 25:616-618
In the split-gate flash memory process, during poly oxidation, the bird's beak encroaches under the SiN film, especially along the poly grain boundary, and that will cause nonuniform floating-gate (FG) spacing, even bridging, which is an obstacle to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f3196a3f0ceeb23ff3b50824e7ec05e
https://doi.org/10.1109/led.2004.833825
https://doi.org/10.1109/led.2004.833825
Autor:
K.C. Tu, Shou-Gwo Wuu, C.N. Pen, C.C. Wang, T. H. Hsieh, K. C. Huang, M. J Wang, C.Y. Pai, K.C. Tzeng, W. C. Chiang, C.Y. Tsai, L.C. Tran, Y.W. Chang, Chia-Shiung Tsai, Hau-Yu Lin, Chun-Yen Chang, H.Y. Hwang, H. C. Chu, Ching-Chun Wang, Y.W. Ting, Y.T. Hsieh, K.W. Chen
Publikováno v:
Proceedings of Technical Program of 2012 VLSI Technology, System and Application.
A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3074420a28837601e2529b3f2301672d
https://doi.org/10.1109/vlsi-tsa.2012.6210164
https://doi.org/10.1109/vlsi-tsa.2012.6210164
Autor:
C.Y. Pai, W.H. Kuo, Shou-Gwo Wuu, I.F. Wang, Sreedhar Natarajan, M. J Wang, H.Y. Hwang, H.W. Chin, H. F. Lee, K.C. Tu, K.C. Tzeng, Y.W. Ting, Chia-Cheng Chen, Atul Katoch, L.C. Tran, Kuo-Chin Huang, Chung-Hao Tsai, Chun-Yen Chang, Arun Achyuthan, Ching-Chun Wang, Kuang-Hsin Chen, Cormac Michael O'connell, H.C. Chu, T.H. Hsieh, Chia-Shiung Tsai, W.C. Chiang
Publikováno v:
2011 International Electron Devices Meeting.
This paper presents industry's smallest 0.035um2 high performance embedded DRAM cell with cylinder-type Metal-Insulator-Metal (MIM) capacitor and integrated into 28nm High-K Metal Gate (HKMG) logic technology. This eDRAM memory features an HKMG CMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08e381b66d952fde10007483fde3063d
https://doi.org/10.1109/iedm.2011.6131608
https://doi.org/10.1109/iedm.2011.6131608