Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Chia-Ping Hsieh"'
Autor:
Chia-Ping Hsieh, 謝佳玶
101
On-line surface profile measurement is very important and practical in the LED industry and semiconductor industry. It has stricter specification of high-speed and high-solution to those components than other parts. In this study, a prototyp
On-line surface profile measurement is very important and practical in the LED industry and semiconductor industry. It has stricter specification of high-speed and high-solution to those components than other parts. In this study, a prototyp
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/75526829190422215178
Publikováno v:
Journal of Electronic Packaging. 144
To overcome the limited operational speed for nanoscaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among
Publikováno v:
Microelectronics Reliability. 83:230-234
The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the port
Publikováno v:
Microsystem Technologies. 24:3233-3240
An efficient 3D profile measurement technique is proposed for in-line full-field inspection of surface feature and defect with high resolution. In this technique, a straight-line grating from a digital light processing illumination source was project
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
There are many portable electronic products made by fan-out wafer/panel level package (FOWLP/FOPLP). The redistribution layer(RDL) design with fine pitch to connect inter each application is used. However, the above packaging products usually face th
Publikováno v:
Applied Physics Express. 14:035504
Stress-induced mechanism and related manifold characteristics from lattice mismatch and harsh self-heating effect (SHE) substantially interact are major concerns of advanced strained Ge p-FinFETs with inherent poor thermal conductivity. This study pr
Autor:
Ming-Han Liao, Pei-Chen Huang, Sen-Wen Cheng, Tsung-Chieh Cheng, Chien-Ping Wang, Chia-Ping Hsieh, Chang-Chun Lee
Publikováno v:
Thin Solid Films. 618:172-177
Given the reduction in size of hole-containing metal-oxide-semiconductor field-effect transistors (pMOSFETs) to break Moore's law, extensive researches have been conducted to improve the performance of nano-scaled devices with the use of strained eng
Autor:
Yan-Yu Liou, Yu-Min Lin, Chau-Jie Zhan, Chien-Ping Wang, Chang-Chun Lee, Tao-Chih Chang, Chia-Ping Hsieh
Publikováno v:
Microelectronic Engineering. 156:24-29
This study presents a process for wafer handling and robust assembly, which is a novel pre-molding technology applied to assembled stacked modules prior to chip thinning. These steps aim to overcome severe challenges of achieving extra-thin thickness
Publikováno v:
Thin Solid Films. 602:78-83
The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal–oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing
Publikováno v:
IEEE Transactions on Electron Devices. 64:646-648
The characteristics of thermal conductivity ( ${k}$ ) with different operated temperatures ( ${T}$ ), material thicknesses ( ${t}$ ), and impurity concentrations ( ${N}$ ) are studied by thermoelectric measurements and developed simulation model for