Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Chi-Hsi Wu"'
Autor:
Chi-Hsi Wu, 吳其錫
101
Among all stages of economic development in Taiwan, public enterprises have been given different policy objectives or playing different roles. Thus, every public enterprise has its own policy objectives. In recent years, public enterprise pe
Among all stages of economic development in Taiwan, public enterprises have been given different policy objectives or playing different roles. Thus, every public enterprise has its own policy objectives. In recent years, public enterprise pe
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/s7x962
Autor:
Chi-Hsi Wu, 吳奇錫
91
Based on mechanical mechanism of an infinitely long, uniform depth of sediment layer, this study constitutes the failure model of the sediment layer and its respective critical slope for the occurrence of debris flow. The results below some l
Based on mechanical mechanism of an infinitely long, uniform depth of sediment layer, this study constitutes the failure model of the sediment layer and its respective critical slope for the occurrence of debris flow. The results below some l
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/4x8267
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36980a93c432694df1cad5c2cc9e3607
https://doi.org/10.1109/ectc.2016.65
https://doi.org/10.1109/ectc.2016.65
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Steady-state and transient thermal performance of a novel memory-integrated 3D-stacking packaging technology, integrated fan-out package-on-package (InFO_PoP), developed for state-of-the-art mobile applications were experimentally characterized using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a750b27f924f623f3b3433e1e863cb9
https://doi.org/10.1109/ectc.2016.277
https://doi.org/10.1109/ectc.2016.277
Autor:
Wu Kai-Chiang, M. J. Lii, Chen Chia-Hsiang, K. C. Hsu, H.J. Kuo, H. P. Pu, C. H. Lee, M.D. Cheng, C. S. Liu, Chi-Hsi Wu, S.L. Chiu, Hao-Yi Tsai, Douglas Yu, Hsin-Chi Chen, Ching-Wen Hsiao, Chih-Hang Tung
Publikováno v:
2010 International Electron Devices Meeting.
The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were use
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ee9f1baa7f18a605ef42f3f565e36fb
https://doi.org/10.1109/iedm.2010.5703472
https://doi.org/10.1109/iedm.2010.5703472
Autor:
M. Jahanbani, Jon D. Cheek, N. Cave, S.j. Lian, Konstantin V. Loiko, Mehul D. Shroff, Chi-Hsi Wu, Stanley M. Filipiak, Xiang-Zheng Bo, H.C. Tuan, M. Azrak, Paul A. Grudowski, Wen-Jya Liang, Vance H. Adams, Sinan Goktepeli, Venkat R. Kolagunta, M. Foisy, John J. Hackenberg
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::33649abd039e0c65218d78c61cea5101
https://doi.org/10.1109/vlsit.2006.1705217
https://doi.org/10.1109/vlsit.2006.1705217
Autor:
S. Filipiak, M. Foisy, John J. Hackenberg, Hsiao-chin Tuan, Xiang-Zheng Bo, Venkat R. Kolagunta, Konstantin V. Loiko, Li-te Lin, Jon Cheek, Paul A. Grudowski, D. Tekleab, Chi-hsi Wu, Vance H. Adams, K.h. Fung
Publikováno v:
2006 IEEE international SOI Conferencee Proceedings.
We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e04e380e001b0d73f4de7f4d79ff883
https://doi.org/10.1109/soi.2006.284411
https://doi.org/10.1109/soi.2006.284411
Autor:
Xiang-Zheng Bo, Grudowski, P., Adams, V., Loiko, K., Tekleab, D., Filipiak, S., Hackenberg, J., Kolagunta, V., Foisy, M., Li-Te Lin, Fung, K.H., Chi-Hsi Wu, Hsiao-Chin Tuan, Cheek, J.
Publikováno v:
2006 IEEE international SOI Conference Proceedings; 2006, p19-20, 2p
Autor:
Grudowski, P., Adams, V., Xiang-Zheng Bo, Loiko, K., Filipiak, S., Hackenberg, J., Jahanbani, M., Azrak, M., Goktepeli, S., Shroff, M., Wen-Jya Liang, Lian, S.J., Kolagunta, V., Cave, N., Chi-Hsi Wu, Foisy, M., Tuan, H.C., Cheek, J.
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.; 2006, p62-63, 2p