Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Chi-Heng Yang"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1235-1244
This paper presents an area-efficient architecture of arbitrary error correction Bose–Chaudhuri–Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39b8b9f64d420f00c3a26bf2be0b31cc
https://doi.org/10.1109/tvlsi.2014.2338309
https://doi.org/10.1109/tvlsi.2014.2338309
Autor:
Wei Lin, Shao-Wei Yen, Chun-Wei Tsao, Yu-Cheng Hsu, Chi-Heng Yang, Lih-Yuarn Ou, Yang Yu-Siang, Tien-Ching Wang, Li-Chun Liang, Kuo-Hsin Lai, Pei-Jung Hsu, Chen Szu-Wei, Kuo Tsai-Hao, An-Chang Liu, Yu-Hsiang Lin
Publikováno v:
ITW
In order to keep reducing the bit cost, NAND Flash memory vendors have changed the NAND Flash technology from 2D to 3D since 2014. Moreover, 3D NAND Flash is becoming the mainstream of the NAND Flash based storage system from 2017. Owing to the stora
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6aeed5cb93783755dac17e352ccb67e9
https://doi.org/10.1109/itw.2017.8278030
https://doi.org/10.1109/itw.2017.8278030
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 58:682-686
According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-effici
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0bd27dad75f5dd18d1a955fccc94dae4
https://doi.org/10.1109/tcsii.2011.2161704
https://doi.org/10.1109/tcsii.2011.2161704
Publikováno v:
ICC
This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e753d0b1a0807d6dddc34d4028545d3
https://doi.org/10.1109/icc.2013.6655246
https://doi.org/10.1109/icc.2013.6655246
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part durin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51930537f987a4c4101558a6fd443298
https://doi.org/10.1109/ipec.2012.6522627
https://doi.org/10.1109/ipec.2012.6522627
Publikováno v:
VLSI-DAT
This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is impleme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cbc500c80890b1b03c49c36aa9456358
https://doi.org/10.1109/vlsi-dat.2012.6212602
https://doi.org/10.1109/vlsi-dat.2012.6212602
Publikováno v:
ICASSP
A double error correcting (DEC) BCH codec is designed for NOR flash memory systems to improve reliability. Due to the latency constraint less than 10 ns, the fully parallel architecture with huge hardware cost is utilized to process both the encoding
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7674b9201ee1278dc0ce397ce0959cef
https://doi.org/10.1109/icassp.2012.6288201
https://doi.org/10.1109/icassp.2012.6288201
Publikováno v:
2011 International Symposium on Integrated Circuits.
In this paper1, an area efficient (224, 216; 4) soft Reed-Solomon (RS) decoder is provided for wireless systems. According to the Chase-II algorithm, 3 least reliable positions (LRPs) are chosen, and the decoded codeword is determined from 8 (=23) ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05d18740d4f7c2d97c7be45891dec4a1
https://doi.org/10.1109/isicir.2011.6131903
https://doi.org/10.1109/isicir.2011.6131903
Publikováno v:
Proceedings of Technical Program of 2012 VLSI Design, Automation & Test; 1/ 1/2012, p1-4, 4p