Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Chi Fung Poon"'
Autor:
Kevin Geary, James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Marc Erett, Chi Fung Poon, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans
Publikováno v:
Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication ISBN: 9783030917401
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66fc987213e120495a7b5896389942d0
https://doi.org/10.1007/978-3-030-91741-8_15
https://doi.org/10.1007/978-3-030-91741-8_15
Autor:
Yipeng Wang, Junho Cho, Eugene Ho, Ma Shaojun, Asma Laraba, Yohan Frans, Daniel Wu, Kee Hian Tan, Wenfeng Zhang, Chi Fung Poon, Ying Cao, Parag Upadhyaya, Winson Lin
Publikováno v:
VLSI Circuits
This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37a5c9766c179cc02c04d20328c043d6
https://doi.org/10.23919/vlsicircuits52068.2021.9492467
https://doi.org/10.23919/vlsicircuits52068.2021.9492467
Autor:
Nakul Narang, Siok Wei Lim, Bruce Xu, Kee Hian Tan, Toan Pham, Wenfeng Zhang, Junho Cho, Geoff Zhang, Chi Fung Poon, Hongtao Zhang, Parag Upadhyaya, Winson Lin, Jin Namkoong, Yohan Frans, Ken Chang, Arianne Roldan
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:18-28
The design of a dual-mode, 19–58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5–29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear eq
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6899a9c54618499489997b2dbff50c2
https://doi.org/10.1109/jssc.2018.2875091
https://doi.org/10.1109/jssc.2018.2875091
Autor:
Hongtao Zhang, Declan Carey, David Mahashin, Neto Pedro W, Ken Chang, Asma Laraba, James Hudner, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Ilias Chlis, Chi Fung Poon, Kay Hearne, Marc Erett, Ronan Casey
Publikováno v:
VLSI Circuits
A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance buffer, and a 56GSa/s 64-way time-interleaved SAR ADC. The receiver achieves 2e-5 BER over a 20
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::967ab14878c9222ce248da2ea38f3449
https://doi.org/10.1109/vlsic.2018.8502436
https://doi.org/10.1109/vlsic.2018.8502436
Autor:
Nakul Narang, Kee Hian Tan, Geoff Zhang, Siok Wei Lim, Chi Fung Poon, Toan Pham, Yohan Frans, Junho Cho, Jin Namkoong, Bruce Xu, Arianne Roldan, Ken Chang, Wenfeng Zhang, Hongtao Zhang, Winson Lin, Parag Upadhyaya
Publikováno v:
ISSCC
Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without significant increase in cost or power per bit. In order to mitigate the cost of infrastructure upgrad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22360100003030795120f09ae8fbde77
https://doi.org/10.1109/isscc.2018.8310207
https://doi.org/10.1109/isscc.2018.8310207
Autor:
Bruce Xu, Elad Alon, Daniel Wu, Chi Fung Poon, Fu-Tai An, Jafar Savoj, Stanley Chen, Parag Upadhyaya, Ken Chang, Ade Bekele, Aman Sewani, Xuewen Jiang, Didem Turker, Kang Wei Lai, Kenny Hsieh, Venna Karthik C
Publikováno v:
VLSIC
This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88d1446cd3b8929154f3a5bffa3b29c2
https://doi.org/10.1109/vlsic.2012.6243811
https://doi.org/10.1109/vlsic.2012.6243811
Autor:
Upadhyaya, Parag, Poon, Chi Fung, Lim, Siok Wei, Cho, Junho, Roldan, Arianne, Zhang, Wenfeng, Namkoong, Jin, Pham, Toan, Xu, Bruce, Lin, Winson, Zhang, Hongtao, Narang, Nakul, Tan, Kee Hian, Zhang, Geoff, Frans, Yohan, Chang, Ken
Publikováno v:
IEEE Journal of Solid-State Circuits; Jan2019, Vol. 54 Issue 1, p18-28, 11p
Autor:
Savoj, Jafar, Hsieh, Kenny, Upadhyaya, Parag, An, Fu-Tai, Bekele, Ade, Chen, Stanley, Jiang, Xuewen, Lai, Kang Wei, Poon, Chi Fung, Sewani, Aman, Turker, Didem, Venna, Karthik, Wu, Daniel, Xu, Bruce, Alon, Elad, Chang, Ken
Publikováno v:
2012 Symposium on VLSI Circuits (VLSIC); 1/ 1/2012, p104-105, 2p
This book is based on the 18 tutorials presented during the 29th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, with specific contri