Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Cheng-Yuh Wu"'
Autor:
Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, CJ Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, YS Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, SA Hwang
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Cheng-Yuh Wu, Jia-Ming Chen, Rory Huang, Yi-Chang Zhuang, Yi-Chuan Chen, Ping Kao, Alex Chiou, Eric Jia-Wei Fang, Shih-Arn Hwang, Yi-Hsuan Lin, Yuwen Tsai, Wen-Wen Hsieh, Cheng-Tien Wan, Ericbill Wang, Harry H. Chen, Sung S.-Y. Hsueh, Barry Chen, Angus Lin, Bo-Jr Huang, Chi-Hsun Chiang
Publikováno v:
ISSCC
A high-speed and power-efficient heterogeneous octa-core CPU complex is realized in a 7nm FinFET process. On-chip sensors that handle guard band in terms of process $(V_{PGB})$, voltage, temperature $(V_{TGB})$, and aging $(V_{AGB})$ are designed for
Autor:
Jason Tsai, Manzur Rahman, Lee-Kee Yong, Rolf Lagerquist, Henry Hsieh, Vincent Lin, Sa Huang, Sudhakar Maruthi, Elly Chiang, Wade Wu, Ericbill Wang, Hsinchen Chen, Ashish Nayak, Anand Rajagopalan, Tao Chen, Gordon Gammie, Curtis Lin, Cheng-Yuh Wu, Hugh Mair, Ramu Madhavaram, Gokulakrishnan Manoharan, Amjad Sikiligiri, Daniel Dia, Efron Ho, Jenny Wiedemeier, Barry Chen, Achuta Thippana, Madhur Jagota, Chi-Jui Chung, Po-Yang Hsu
Publikováno v:
ISSCC
This paper describes a new CPU subsystem featured in a 5G mobile SoC. The High-Performance (HP) core achieves a 3GHz clock frequency with full production yield across the fabrication range and operating environment. In contrast to previously publishe
Autor:
Ray Tzeng, Cheng-Yuh Wu, Taner Dosluoglu, Chi-Hsueh Wang, Jin Son, David Yen, Hugh Mair, Girishankar Gurumurthy, Yi-Chang Zhuang, Wuan Kuo, Yuwen Tsai, Hung-Wei Wang, Ue Fu, Rolf Lagerquist, Kent Li, Achuta Thippana, Sumanth Gururajarao, Tony Hsieh, Ping Kao, Alice Wang, Mark Shane Peng, Gordon Lin, Jengding Wu, Anatoly Gelman, Daniel Dia, Lin Wen-Yi, Uming Ko, Gordon Gammie, Manzur Rahman, Ericbill Wang
Publikováno v:
ISSCC
This paper describes logic and circuit design features of a heterogeneous tri-cluster deca-core CPU complex incorporated into a 10nm FinFET mobile SoC for smartphone applications. Similar to Helio X20 [1], the Deca-Core compute function contains thre