Výsledky vyhledávání - "Chen-Shiun Lee"

Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may indu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cdb6a20e453a616bf09e0e03effcfdf9
https://doi.org/10.1109/tsm.2021.3065405

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TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning

Autor: Sying-Jyan Wang, Nova Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Leon Chou, Chen-Shiun Lee, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Leon Li-Yang Chen

Publikováno v: ITC

We propose a machine learning based method targeted for accurate wafer defect map classification. The proposed method is referred to as TestDNA-E, as it applies ensemble learning based on improved TestDNA features. Experimental results show that the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4790f28803e5978df54cf0c322fa7798
https://doi.org/10.1109/itc44778.2020.9325237

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Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

Autor: Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Peter Yi-Yu Liao, Leon Chou, Ji-Wei Li, Andrew Yi-Ann Huang, Hsing-Chung Liang, Jwu E. Chen, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Chen-Shiun Lee

Publikováno v: DATE

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::388720e0b20bd7e63d28f4b6b35350e2
https://doi.org/10.23919/date48585.2020.9116546

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TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning

Autor: Xu-Hao Jiang, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Leon Chou, Andrew Yi-Ann Huang, Chen-Shiun Lee, Katherine Shu-Min Li, Sying-Jyan Wang

Publikováno v: ITC

Wafer defect maps exhibit spatial failure pattern recognition for root cause analysis to improve defect diagnosis resolution and yield learning conventionally. We apply further product-driven test items to propose a wafer-level test methodology to ge

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::01daac3561faf61999037c2e85a23db4
https://doi.org/10.1109/itc44170.2019.9000166

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