Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Chen Shuo-Mao"'
Publikováno v:
IRPS
Reliability test efficiency and accuracy are both important to technology development. In this study, we develop a new gate oxide reliability test method, called tunable ramp voltage stress (TRVS). It can perform a quick gate oxide reliability test l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8507a898268e1076c5c00a4b08a3760e
https://doi.org/10.1109/irps46558.2021.9405144
https://doi.org/10.1109/irps46558.2021.9405144
Autor:
Y. S. Tsai, Subhadeep Mukhopadhyay, D. S. Huang, J. H. Lee, I. K. Chen, Chen Shuo-Mao, Jun He, Ryan Lu
Publikováno v:
IRPS
This work presents a systematic study of the off-state drain bias time dependent dielectric breakdown (TDDB) mechanism, especially for the short channel transistors in advanced FinFET technologies. The sub-threshold leakage current was found to play
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fab6ef0c793056359b2fd914faef6167
https://doi.org/10.1109/irps.2018.8353575
https://doi.org/10.1109/irps.2018.8353575
Autor:
Jen-Cheng Liu, Subhadeep Mukhopadhyay, Ryan Lu, Jun He, J. H. Lee, Y. F. Wang, Chen Shuo-Mao, Y.-H. Lee, Y. S. Tsai
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
Presence of any erroneous leakage current source, due to any intrinsic or extrinsic device failure, can severely impact the 6-Transistor (6T) SRAM performance. This study introduces a ‘Pseudo-Leakage’ (PL) current source in the SRAM 6T circuit an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::827109616dfab05c3737342d87679d67
https://doi.org/10.1109/iedm.2017.8268379
https://doi.org/10.1109/iedm.2017.8268379
Autor:
En-Hsiang Yeh, Cheng-chieh Hsieh, John Yeh, Shang-Yun Hou, Jing-Cheng Lin, Ming-Yen Chiu, Shin-puu Jeng, Chewn-Pu Jou, Douglas Yu, Chuei-Tang Wang, Li-Hsien Huang, Tzu-Jin Yeh, Chen Shuo-Mao, Huan-Neng Chen, Jui-Pin Hung, Tsung-Shu Lin, Feng Wei Kuo, Christianto Chih-Ching Liu
Publikováno v:
2012 International Electron Devices Meeting.
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) syste
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08a6cdbb29a58afdf56ee27ef44ca5c4
https://doi.org/10.1109/iedm.2012.6479039
https://doi.org/10.1109/iedm.2012.6479039
Autor:
C.F. Nieh, Huang-Chung Cheng, Y.M. Sheu, K.C. Ku, Tze-Liang Lee, Mong-Song Liang, M.H. Yu, H.Y. Chu, H. Hisa, C.W. Tsai, J.H. Li, C.H. Chen, Y.L. Wang, Chen Shuo-Mao, H.H. Lin
Publikováno v:
2006 International Electron Devices Meeting.
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a87e4e535f4400f428711bf2907bcc8
https://doi.org/10.1109/iedm.2006.346919
https://doi.org/10.1109/iedm.2006.346919
Publikováno v:
In Solid State Electronics August 2008 52(8):1140-1144
Akademický článek
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Akademický článek
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Autor:
Liu, Christianto C., Chen, Shuo-Mao, Kuo, Feng-Wei, Chen, Huan-Neng, Yeh, En-Hsiang, Hsieh, Cheng-Chieh, Huang, Li-Hsien, Chiu, Ming-Yen, Yeh, John, Lin, Tsung-Shu, Yeh, Tzu-Jin, Hou, Shang-Yun, Hung, Jui-Pin, Lin, Jing-Cheng, Jou, Chewn-Pu, Wang, Chuei-Tang, Jeng, Shin-Puu, Yu, Douglas C. H.
Publikováno v:
2012 International Electron Devices Meeting; 2012, p1.4-14.1.4, 0p