Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Chee Houe Khong"'
Autor:
Dim-Lee Kwong, Venky Sundaram, John H. Lau, Xiaowu Zhang, Yue Ying Ong, Soon Wee Ho, Chee Houe Khong, R.R. Tummula, Aditya Kumar, V. Kripesh, Qing Xin Zhang, Georg Meyer-Berg
Publikováno v:
Sensors and Actuators A: Physical. 156:2-7
Because of 3D integration, thickness of Silicon wafer is thinner and thinner. For thin silicon ICs, challenges in wafer thinning, handling and assembly process increase. The piezoresistive stress sensors studied in this paper are for experimental pur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9c42fbf1f5ee56855ea27724b712b0b
https://doi.org/10.1016/j.sna.2009.01.024
https://doi.org/10.1016/j.sna.2009.01.024
Autor:
Nagendra Sekhar Vasarla, Srinivasa Rao Vempati, Eric Woon Yik Yong, Chee Houe Khong, Guan Kian Lau, C. Teo, Khan O K Navas, Hyoung Joon Kim, Vincent Lee, D.M. Fernandez, David Ho, Ser Choong Chong
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
In this paper, we focus how to overcome process challenges, such as die shift and warpage, and to fabricate thin embedded wafer level packages (EMWLPs) with 200μm-thick eventually. The initial warpage of reconfigured wafer after post mold curing (PM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f830fbb2c44bb5b18e9a2ff10af81bc
https://doi.org/10.1109/ectc.2011.5898495
https://doi.org/10.1109/ectc.2011.5898495
Autor:
Damaruganath Pinjala, Sharon Pei Siang Lim, Xiaowu Zhang, Ying Ying Lim, V. Kripesh, N. Khan, Chee Houe Khong, Soon Wee Ho, Leong Ching Wai, Andy Fenner
Publikováno v:
2010 12th Electronics Packaging Technology Conference.
A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de917d5c542950f76b81bdf3a14a68ce
https://doi.org/10.1109/eptc.2010.5702632
https://doi.org/10.1109/eptc.2010.5702632
Autor:
Ser Choong Chong, Chee Houe Khong, Vempati Srinivasa Rao, Calvin Teo Wei Liang, Keith Lim Cheng Sing, Vincent Lee Wen Sheng, Jaesik Lee, Kim Hyoung Joon, David Ho Soon Wee
Publikováno v:
2010 12th Electronics Packaging Technology Conference.
Embedded Wafer Level Package (eWLP) is designed and developed. The eWLP consists of one silicon die encapsulated with a mold compound and its size is 12mm × 12mm × 0.2mm. The assembly process of eWLP consists of reconfiguration of the dies on an ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d28c1976016c829714b530c9424b9ab1
https://doi.org/10.1109/eptc.2010.5702696
https://doi.org/10.1109/eptc.2010.5702696
Autor:
Chee Houe Khong, W. S. Lee, Soon Wee Ho, C. H. Toh, Li Shiah Lim, S Nathapong, S. P. Chew, T. T. Chua, C. Ng, Hongyu Li, S. L. Kriangsak, X. F. Pang, Ebin Liao
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can redu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73ab3cd014594ce0750fae486279e72d
https://doi.org/10.1109/ectc.2010.5490728
https://doi.org/10.1109/ectc.2010.5490728
Autor:
Aibin Yu, Carl Chen, Xiaowu Zhang, Chien-Feng Chan, Chih-Ming Huang, V. Kripesh, Chee Houe Khong, Chi-Hsin Chiu, Scott Chen, Damaruganath Pinjala, Dim-Lee Kwong, Chun-Chieh Chao
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
The submodeling technique is a powerful analysis tool. The method promotes more accurate analysis and also helps enhance productivity. It has been shown that by using displacement-force cut boundary condition method, it can be made even more versatil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f72e759889359795135289a4858f288d
https://doi.org/10.1109/eptc.2009.5416481
https://doi.org/10.1109/eptc.2009.5416481
Autor:
K. Y. Au, John H. Lau, Ying Ying Lim, Chee Houe Khong, B. P. Liew, Srinivasa Rao Vempati, Robert Erich, Susanto Tanary, Juan Milla, Nandar Su, Andy Fenner, Kripesh Vaidyanathan
Publikováno v:
2009 59th Electronic Components and Technology Conference.
Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a62a5bda6c525906de371a609003107b
https://doi.org/10.1109/ectc.2009.5074132
https://doi.org/10.1109/ectc.2009.5074132
Autor:
Dim-Lee Kwong, Chee Houe Khong, Xiaowu Zhang, John H. Lau, Venky Sundaram, V. Kripesh, R.R. Tummula, Georg Meyer-Berg
Publikováno v:
2008 10th Electronics Packaging Technology Conference.
The effect of thinning down the chip thickness, will affect the stress pattern in the chip and causes the chip to deform locally when the thickness of the chip is thinner than a certain critical value. Such a local deformation may cause sharp gradien
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94cc6a121b814a1b3b6bf46f8b141e33
https://doi.org/10.1109/eptc.2008.4763440
https://doi.org/10.1109/eptc.2008.4763440
Autor:
Chee Houe Khong, Chee Wei Tan, Joey Chai, Jing Li, Geri Endrio Tangdiongga, Dim-Lee Kwong, Jing Zhang, Gongyue Tang, Xiaowu Zhang, Teck Guan Lim, P.V. Ramana, John H. Lau, Jayakrishnan Chandrappan, Ying Ying Lim
Publikováno v:
SPIE Proceedings.
In this study, a low-cost (with bare chips) and high (optical, electrical, and thermal) performance optoelectronic system with a data rate of 10Gbps is designed and analyzed. This system consists of a rigid printed circuit board (PCB) made of FR4 mat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84eaab6f8980ce0d145bec8c363b12ef
https://doi.org/10.1117/12.764032
https://doi.org/10.1117/12.764032
Autor:
Hyoung Joon Kim, Ser Choong Chong, Ho, D.S.W., Yong, E.W.Y., Chee Houe Khong, Teo, C.W.L., Fernandez, D.M., Guan Kian Lau, Vasarla, N.S., Lee, V.W.S., Vempati, S.R., Navas, K.O.K.
Publikováno v:
2011 IEEE 61st Electronic Components & Technology Conference (ECTC); 2011, p78-83, 6p