Zobrazeno 1 - 10
of 110
pro vyhledávání: '"Chau‐Jie Zhan"'
Autor:
Yuan-Wei Chang, Chia-chia Hu, Hsin-Ying Peng, Yu-Chun Liang, Chih Chen, Tao-chih Chang, Chau-Jie Zhan, Jing-Ye Juang
Publikováno v:
Scientific Reports, Vol 8, Iss 1, Pp 1-10 (2018)
Abstract Microbumps in three-dimensional integrated circuit now becomes essential technology to reach higher packaging density. However, the small volume of microbumps dramatically changes the characteristics from the flip-chip (FC) solder joints. Fo
Externí odkaz:
https://doaj.org/article/95d9bab85d2d47cb8eb43dd4186fb7ff
Autor:
Chau-Jie Zhan, 詹朝傑
95
This study aims to investigate the microstructure, creep behavior and high temperature oxidation behavior of novel high niobium-containing Ti-40Al-xNb (x=10,12,15,16) intermetallic alloy. The microstructure of the as-cast Ti-40Al-10Nb alloy c
This study aims to investigate the microstructure, creep behavior and high temperature oxidation behavior of novel high niobium-containing Ti-40Al-xNb (x=10,12,15,16) intermetallic alloy. The microstructure of the as-cast Ti-40Al-10Nb alloy c
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/25203666282663344489
Autor:
Yan-Yu Liou, Yu-Min Lin, Chau-Jie Zhan, Chien-Ping Wang, Chang-Chun Lee, Tao-Chih Chang, Chia-Ping Hsieh
Publikováno v:
Microelectronic Engineering. 156:24-29
This study presents a process for wafer handling and robust assembly, which is a novel pre-molding technology applied to assembled stacked modules prior to chip thinning. These steps aim to overcome severe challenges of achieving extra-thin thickness
Publikováno v:
Vacuum. 118:152-160
Three-dimensional integrated circuit (3D-IC) packaging has attracted considerable research interest because it allows the integration of heterogeneous functions among stacked chips. The thermal mismatch stresses induced by thermal cycling loads in th
Autor:
Yu-Mei Cheng, Ren-Shing Cheng, Li-Ling Liao, Jui-Feng Hung, Yu-Lin Chao, Ra-Min Tain, Ming-Ji Dai, Yu-Wei Huang, Heng-Chieh Chien, Chun-Hsien Chien, Wei-Chung Lo, Chau-Jie Zhan, Ching-Kuan Lee, Ming-Jer Kao, Sheng-Tsai Wu, John H. Lau
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 4:1407-1419
In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of
Publikováno v:
Microelectronic Engineering. 120:138-145
To enhance the assembly quality and mechanical reliability of microbumps during the stacking process of multiple thin chips and during temperature cycling tests, a novel wafer-level underfill (WLUF) fabrication technique has been proposed to resolve
Publikováno v:
Materials Letters. 137:136-138
The electromigration behavior was investigated in 18-μm SnAg microbumps at 150 1C. The monitored resistance increase abruptly soon after the current stressing of 4.610 4 A/cm 2 was applied but the resistance rose much slower after a certain period o
Autor:
Chih-Sheng Wu, Tai-Hung Chen, Kuo-Shu Kao, Tsung-Fu Yang, John H. Lau, Chau-Jie Zhan, Chang-Chun Lee, C. W. Fang
Publikováno v:
Microelectronic Engineering. 107:101-106
Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the
Autor:
Yuan Wei Chang, Jin-Ye Juang, H. Y. Peng, Chih Chen, Annie T. Huang, Chau-Jie Zhan, Tao-Chih Chang, R. W. Yang
Publikováno v:
Microelectronics Reliability. 53:41-46
To keep up with the demand of continuous increase in device densities, the integration of three-dimensional integrated circuits (3D-IC) has become the most probable solution, and the utilization of ultra-fine-pitch microbump has emerged as an essenti
Autor:
Kuo-Chyuan Chen, Hsiang-Hung Chang, Yuan-Chang Lee, Ching-Kuan Lee, Yung Jean Rachel Lu, Jen-Chun Wang, Chia-Wen Fan, Wen-Wei Shen, Huan-Chun Fu, Chau-Jie Zhan
Publikováno v:
2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
In this paper, we investigate reliability testing for a glass interposer. The test vehicle is an assembled glass interposer with a chip, a BT substrate. The structure of a glass interposer with two redistribution layers (RDLs) on the front-side and o