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pro vyhledávání: '"Charles F. Webb"'
Autor:
Charles F. Webb
Publikováno v:
IEEE Micro. 41:68-70
The microprocessor revolution, of which this issue marks the 50th anniversary, drove remarkable innovations in instruction set architecture, microarchitecture, and system design, some of which continue to evolve in current research and commercial pro
Autor:
Christian Jacobi, Charles F. Webb
Publikováno v:
IEEE Micro. 40:50-58
IBM Z is both the oldest and among the most modern of computing platforms. Launched as S/360 in 1964, the mainframe became synonymous with large-scale computing for business and remains the workhorse of enterprise computing for businesses worldwide.
Autor:
Guenter Mayer, Thomas Strach, Yiu-Hing Chan, Gerard M. Salem, Ayan Datta, Doug Malone, David L. Rude, Adam R. Jatkowski, James D. Warnock, Donald W. Plass, Anne E. Gattiker, C-L Kevin Shum, Charles F. Webb, Jeffrey A. Zitz, Aditya Bansal, L. Sigal, Gerald Strevig, Pak-Kin Mak, Howard H. Smith, Ruchir Puri, S. Carey, Hubert Harrer, M. Mayo, Huajun Wen, Yuen Chan
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:9-18
This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-
Autor:
Charles F. Webb
Publikováno v:
IEEE Micro. 28:19-29
Autor:
T.J. McPherson, J. D. MacDougall, John Stephen Liptay, R. Averill, J.A. Navarro, C.A. Krygowski, C. Kevin Shum, B.C. Giamei, Eric M. Schwarz, M.A. Check, T.J. Slegel, Barry Watson Krumm, W.H. Li, Charles F. Webb
Publikováno v:
IEEE Micro. 19:12-23
The IBM S/390 G5 microprocessor in IBM's newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such
Autor:
C. Price, W.V. Houtt, James D. Warnock, M.S. Farrell, M. Mayo, R. Averill, C.J. Anderson, Brian W. Curran, Kenneth L. Shepard, B. Wile, Phillip J. Restle, T.J. Slegel, Barry Watson Krumm, D. Beece, Ching-Te Chuang, L. Sigal, Yuen H. Chan, T. Nguyen, John Stephen Liptay, Philip G. Emma, Charles F. Webb, Peter J. Camporese, Eric M. Schwarz
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:1665-1675
A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-/spl mu/m L/sub eff/ CMOS technology with five layers of metal and tungsten local interconnect.
Autor:
M. Mayo, Chung-Lung Shum, Huajun Wen, Guenter Mayer, Thomas Strach, D. Malone, Y.-H. Chan, James D. Warnock, S. Carey, L. Sigal, Gerald Strevig, Donald W. Plass, Ruchir Puri, Gerard M. Salem, Anne E. Gattiker, Yiu-Hing Chan, Aditya Bansal, Hubert Harrer, Ayan Datta, Adam R. Jatkowski, Charles F. Webb, Pak-Kin Mak, David L. Rude
Publikováno v:
ISSCC
The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improv
Autor:
Brian W. Curran, Y.-H. Chan, S. Carey, Patrick J. Meaney, M. Mayo, L. Sigal, Guenter Mayer, Michael Fee, Lee Evan Eisen, Eric M. Schwarz, Pak-Kin Mak, D. Malone, Frank Malgioglio, Howard H. Smith, T. J. McPherson, Huajun Wen, Thomas Strach, Michael H. Wood, William V. Huott, M. J. Saccamango, James D. Warnock, S. Weitzel, Yuen H. Chan, David L. Rude, R. Averill, Donald W. Plass, Charles F. Webb
Publikováno v:
ISSCC
The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm des
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540223771
SAMOS
SAMOS
This paper describes our state-of-the-art design flow used for specification, implementation and verification of a 10 million gates ASIC System-on-Chip (SoC) for a Sonet/SDH application. We present our tools and methodologies currently used and/or be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d5b2bb6bb200b0d62831c2159057efc
https://doi.org/10.1007/978-3-540-27776-7_11
https://doi.org/10.1007/978-3-540-27776-7_11
Autor:
Barry Watson Krumm, Gregory A. Northrop, Y.H. Chan, C. Krygowski, Timothy G. McNamara, T. J. McPherson, Eric M. Schwarz, John Stephen Liptay, M. Check, Dale Eugene Hoffman, D. Webber, M. Mayo, K. Barkley, Y.-H. Chan, S. Carey, R. Averill, Charles F. Webb, William V. Huott, L.S.T. Siegel, Patrick M. Williams
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and an IEEE compliant binary floating-point. The microprocessor operates at 600 MHz a