Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Chao-Wen Tzeng"'
Autor:
CHAO-WEN TZENG, 曾昭文
102
Because the air force arise excessively many self-injury cases, and many outstanding soldiers want to retire from the army, it gives rise to the national military huaman resource to be uneven. How the political war personnel bring what he ha
Because the air force arise excessively many self-injury cases, and many outstanding soldiers want to retire from the army, it gives rise to the national military huaman resource to be uneven. How the political war personnel bring what he ha
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/eum6xn
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:621-630
In this paper, we propose a parameterized digitally controlled oscillator that can produce oscillating-clock signal with the tunable frequency covering an entire designated range. Moreover, we formulate the all-digital phase-locked loop optimization
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61ceeb34dae24d30a6a6cd40105e47f9
https://doi.org/10.1109/tvlsi.2013.2248070
https://doi.org/10.1109/tvlsi.2013.2248070
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:2240-2249
For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12ece8f2a8eb5eaf4f8ecd4283cc6468
https://doi.org/10.1109/tvlsi.2012.2230454
https://doi.org/10.1109/tvlsi.2012.2230454
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 60:908-917
This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-DLL) and a Dual Locking Mechanism (DLM), this method can be used to maintain a gl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4ce935087c61aeda98b3cdec6a34171
https://doi.org/10.1109/tcsi.2012.2215394
https://doi.org/10.1109/tcsi.2012.2215394
Autor:
Ching-Cheng Tien, Hsi-Pin Ma, Tsung-Yeh Li, Po-Chiun Huang, Cheng-Wen Wu, Hsuan-Jung Hsu, Jing-Jia Liou, Chih-Tsun Huang, Chao-Wen Tzeng, Shi-Yu Huang, Chih-Hu Wang, Jenn-Chyou Bor
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:329-341
Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d545ba66d323e75ee33783117de52c7a
https://doi.org/10.1109/tvlsi.2012.2187223
https://doi.org/10.1109/tvlsi.2012.2187223
Autor:
Chao-Wen Tzeng, Shi-Yu Huang
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:834-839
In modern scan architecture, it is often desirable to compact the output response without jeopardizing the diagnostic resolution. In this paper, we propose an output masking scheme to meet such a stringent requirement. We consider a practical scenari
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb58561f2db8625017331ab3ec4f5391
https://doi.org/10.1109/tcad.2010.2043758
https://doi.org/10.1109/tcad.2010.2043758
Autor:
Chao-Wen Tzeng, Shi-Yu Huang
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:1756-1766
This paper presents an X-fill scheme that properly utilizes the don't-care bits in test patterns to simultaneously reduce the test time as well as the test power (including both capture power and shifting power). This scheme, called Quick-and-Cool X-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::efc8314d1a77c2683d8cf678bf3c4e76
https://doi.org/10.1109/tcad.2009.2030353
https://doi.org/10.1109/tcad.2009.2030353
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:764-769
This paper presents a layout-based methodology to predict the exact physical location of a bridging defect inside a standard cell. It involves a number of techniques. First of all, most likely intracell bridging defects are identified through layout
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::681e862e161f4c2d4363ec8d7165ef2d
https://doi.org/10.1109/tcad.2009.2017216
https://doi.org/10.1109/tcad.2009.2017216
Autor:
Shi-Yu Huang, Chao-Wen Tzeng
Publikováno v:
IEEE Design & Test of Computers. 25:132-140
Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::522fac15701bd3faa9413fff6db14711
https://doi.org/10.1109/mdt.2008.55
https://doi.org/10.1109/mdt.2008.55
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 13:1-27
Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc2094bc2de6e92e473308f051621ff3
https://doi.org/10.1145/1297666.1297675
https://doi.org/10.1145/1297666.1297675