Zobrazeno 1 - 10
of 28
pro vyhledávání: '"Chao-Chang Chiu"'
Autor:
Chao-Chang Chiu, 邱昭彰
98
The issue of energy saving and carbon reduction is more and more important on circuit design. Phase-locked loop (PLL) is one of the important blocks in communication system. Thus, the power consumption of PLL is not able to ignore. To reduce
The issue of energy saving and carbon reduction is more and more important on circuit design. Phase-locked loop (PLL) is one of the important blocks in communication system. Thus, the power consumption of PLL is not able to ignore. To reduce
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/72196391495539704346
Autor:
Ke-Horng Chen, Hsin Chen, Chao-Chang Chiu, Tsung-Hsun Tsai, Tsung-Yen Tsai, Shang-Hsien Yang, Ying-Hsi Lin, Jian-Ru Lin
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:1003-1012
In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltage
Autor:
Chih-Wei Chang, Shian-Ru Lin, Che-Hao Meng, Ke-Horng Chen, Chao-Chang Chiu, Tsung-Yen Tsai, Shang-Hsien Yang, Ying-Hsi Lin
Publikováno v:
IEEE Transactions on Industrial Electronics. 63:5912-5920
A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the m
Autor:
Chen-Min Chen, Ke-Horng Chen, Chih-Wei Chang, Chao-Chang Chiu, Shang-Hsien Yang, Che-Hao Meng
Publikováno v:
IEEE Transactions on Power Electronics. 31:3118-3127
The proposed overall power management in laptops can improve overall power conversion efficiency by the flexible voltage scaling (FVS) technique in cooperation with conventional dynamic voltage scaling (DVS) technique. The FVS technique separates the
Publikováno v:
ISSCC
In power-management integrated circuits (PMIC) for smart phones, cascaded buck and low-dropout (LDO) regulators with N-type power MOSFETs are commonly utilized for high conversion efficiency, power quality and high-density integration as shown in Fig
Autor:
Chen Chao-Cheng Lee, Chao-Chang Chiu, Ke-Horng Chen, Moris Lin, Tsung-Yen Tsai, Po Hsien Huang, Ying-Hsi Lin
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:59-69
The proposed resistance-locked loop (RLL) can achieve high PSRR of $-$ 16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthe
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:2786-2795
The self-calibrated knee voltage detector (SC-KVD) for electrical isolation primary side charger applications is proposed. The removal of the feedback network which is used in conventional designs and occupies at least 30 mm 2 can save PCB area up to
Publikováno v:
IEEE Transactions on Power Electronics. 29:4959-4969
The proposed quasiresonant control scheme can be widely used in a dc–dc flyback converter because it can achieve high efficiency with minimized external components. The proposed dynamic frequency selector improves conversion efficiency especially a
Autor:
Ying-Hsi Lin, Tzu-Chi Huang, Chao-Cheng Lee, Tsung-Yen Tsai, Chao-Chang Chiu, Cheng-Chen Yang, Long-Der Chen, Chen-Chih Huang, Ke-Horng Chen, Shen-Yu Peng, Yu-Huei Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2649-2661
This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorit
Autor:
Ying-Hsi Lin, Alex Chun-Hsien Wu, Ke-Horng Chen, Yu-Huei Lee, Chao-Chang Chiu, Shih-Wei Wang, Chao-Cheng Lee, Chen-Chih Huang, Tsung-Yen Tsai, Shen-Yu Peng
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1018-1030
A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The p