Výsledky vyhledávání - "Chao-Chang Chiu"

High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger

Autor: Ke-Horng Chen, Hsin Chen, Chao-Chang Chiu, Tsung-Hsun Tsai, Tsung-Yen Tsai, Shang-Hsien Yang, Ying-Hsi Lin, Jian-Ru Lin

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 64:1003-1012

In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltage

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6f3c512c734ded4f6b151f31cbe45392
https://doi.org/10.1109/tcsi.2016.2624743

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A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction

Autor: Chih-Wei Chang, Shian-Ru Lin, Che-Hao Meng, Ke-Horng Chen, Chao-Chang Chiu, Tsung-Yen Tsai, Shang-Hsien Yang, Ying-Hsi Lin

Publikováno v: IEEE Transactions on Industrial Electronics. 63:5912-5920

A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the m

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4f79e18324466c4153903d7e590e7ea1
https://doi.org/10.1109/tie.2016.2527630

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87% Overall High Efficiency and 11 μA Ultra-Low Standby Current Derived by Overall Power Management in Laptops With Flexible Voltage Scaling and Dynamic Voltage Scaling Techniques

Autor: Chen-Min Chen, Ke-Horng Chen, Chih-Wei Chang, Chao-Chang Chiu, Shang-Hsien Yang, Che-Hao Meng

Publikováno v: IEEE Transactions on Power Electronics. 31:3118-3127

The proposed overall power management in laptops can improve overall power conversion efficiency by the flexible voltage scaling (FVS) technique in cooperation with conventional dynamic voltage scaling (DVS) technique. The FVS technique separates the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6b7f931e14ebd2587a641e4f94e75840
https://doi.org/10.1109/tpel.2015.2450746

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94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone

Autor: Chang Chih-Wei, Chen Wei-Chung, Chao-Chang Chiu, Huang Tzu-Chi, Hsu Kuo-Chun

Publikováno v: ISSCC

In power-management integrated circuits (PMIC) for smart phones, cascaded buck and low-dropout (LDO) regulators with N-type power MOSFETs are commonly utilized for high conversion efficiency, power quality and high-density integration as shown in Fig

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cfefd0e8b0eebd7a3951b9ffbe7836ac
https://doi.org/10.1109/isscc.2018.8310371

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A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement

Autor: Chen Chao-Cheng Lee, Chao-Chang Chiu, Ke-Horng Chen, Moris Lin, Tsung-Yen Tsai, Po Hsien Huang, Ying-Hsi Lin

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 62:59-69

The proposed resistance-locked loop (RLL) can achieve high PSRR of $-$ 16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthe

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::aca13d97a83a2f8f1b03155f3a35b6b5
https://doi.org/10.1109/tcsi.2014.2342380

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Self-Calibrated Knee Voltage Detector With 99.65% High Accuracy for AC Charger System in 0.5 $\mu{\rm m}$ 500 V UHV Process

Autor: Hsiang An Yang, Chao Chang Chiu, Moris Lin, Chih-Wei Chang, Che Hao Meng, Ke-Horng Chen

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 61:2786-2795

The self-calibrated knee voltage detector (SC-KVD) for electrical isolation primary side charger applications is proposed. The removal of the feedback network which is used in conventional designs and occupies at least 30 mm 2 can save PCB area up to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::06312b4b0a17d13054dfd73cdb4313af
https://doi.org/10.1109/tcsi.2014.2333683

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Quasiresonant Control With a Dynamic Frequency Selector and Constant Current Startup Technique for 92% Peak Efficiency and 85% Light-Load Efficiency Flyback Converter

Autor: Moris Lin, Chao-Chang Chiu, Yu-Chai Kang, Ke-Horng Chen, Jinq-Min Lin, Chih-Pu Yeh

Publikováno v: IEEE Transactions on Power Electronics. 29:4959-4969

The proposed quasiresonant control scheme can be widely used in a dc–dc flyback converter because it can achieve high efficiency with minimized external components. The proposed dynamic frequency selector improves conversion efficiency especially a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::774139ae24c076eb1ba78536891dce77
https://doi.org/10.1109/tpel.2013.2263040

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Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings

Autor: Ying-Hsi Lin, Tzu-Chi Huang, Chao-Cheng Lee, Tsung-Yen Tsai, Chao-Chang Chiu, Cheng-Chen Yang, Long-Der Chen, Chen-Chih Huang, Ke-Horng Chen, Shen-Yu Peng, Yu-Huei Lee

Publikováno v: IEEE Journal of Solid-State Circuits. 48:2649-2661

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8612a8f78733b06c138e0847d2639411
https://doi.org/10.1109/jssc.2013.2274885

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A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

Autor: Ying-Hsi Lin, Alex Chun-Hsien Wu, Ke-Horng Chen, Yu-Huei Lee, Chao-Chang Chiu, Shih-Wei Wang, Chao-Cheng Lee, Chen-Chih Huang, Tsung-Yen Tsai, Shen-Yu Peng

Publikováno v: IEEE Journal of Solid-State Circuits. 48:1018-1030

A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::07479eb8b5f10012d62702899b4d508a
https://doi.org/10.1109/jssc.2013.2237991

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A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System

Autor: Yu-Huei Lee, Ke-Horng Chen, Chao-Chang Chiu, Chen-Chih Huang, Ying-Hsi Lin, Shen-Yu Peng, Chao-Cheng Lee, Tsung-Yen Tsai

Publikováno v: IEEE Journal of Solid-State Circuits. 47:2563-2575

A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for s

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6295c3d0567784945e6e1a3e3bea9b63
https://doi.org/10.1109/jssc.2012.2211671

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