Zobrazeno 1 - 10
of 100
pro vyhledávání: '"Chanro Park"'
Autor:
Fabia Farlin Athena, Omobayode Fagbohungbe, Nanbo Gong, Malte J. Rasch, Jimmy Penaloza, SoonCheon Seo, Arthur Gasasira, Paul Solomon, Valeria Bragaglia, Steven Consiglio, Hisashi Higuchi, Chanro Park, Kevin Brew, Paul Jamison, Christopher Catano, Iqbal Saraf, Claire Silvestre, Xuefeng Liu, Babar Khan, Nikhil Jain, Steven McDermott, Rick Johnson, I. Estrada-Raygoza, Juntao Li, Tayfun Gokmen, Ning Li, Ruturaj Pujari, Fabio Carta, Hiroyuki Miyazoe, Martin M. Frank, Antonio La Porta, Devi Koty, Qingyun Yang, Robert D. Clark, Kandabara Tapily, Cory Wajda, Aelan Mosden, Jeff Shearer, Andrew Metz, Sean Teehan, Nicole Saulnier, Bert Offrein, Takaaki Tsunomura, Gert Leusink, Vijay Narayanan, Takashi Ando
Publikováno v:
Frontiers in Electronics, Vol 4 (2024)
Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorith
Externí odkaz:
https://doaj.org/article/251ccb96d4dd435e83908250513bf0fa
Autor:
Tenko Yamashita, Andrew M. Greene, Kangguo Cheng, Frougier Julien, Miaomiao Wang, Balasubramanian S. Pranatharthi Haran, Sanjay Mehta, Nicolas Loubet, Richard A. Conti, Son Nguyen, Zuoguang Liu, Jingyun Zhang, Heng Wu, Juntao Li, Chanro Park, Rama Divakaruni
Publikováno v:
IEEE Transactions on Electron Devices. 67:5355-5361
We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active
Autor:
Rama Divakaruni, Andrew M. Greene, Sanjay Mehta, Miaomiao Wang, Richard A. Conti, Balasubramanian S. Haran, Heng Wu, Zuoguang Liu, Son Nguyen, Juntao Li, Tenko Yamashita, Kangguo Cheng, Frougier Julien, Nicolas Loubet, Chanro Park, Jingyun Zhang
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transi
Autor:
Hosadurga Shobha, Tenko Yamashita, Chanro Park, Huiming Bu, R. Divakaruni, V. Basker, C. Adams, Dechao Guo, Jingyun Zhang, Lan Yu, Pietro Montanini, X.-H. Liu, A. Arceo De La Pena, Frougier Julien, Kai Zhao, Ruqiang Bao, Robert R. Robison, Nicolas Loubet, Balasubramanian S. Pranatharthi Haran, Muthumanickam Sankarapandian, Xin Miao, James Chingwei Li, Richard A. Conti, Tian Shen, Junli Wang, Praveen Joseph, Huimei Zhou, Koji Watanabe, Reinaldo A. Vega, Shanti Pancharatnam, Ruilong Xie, Curtis Durfee, A. Gaul, Daniel J. Dechene, Andrew M. Greene, Robin Chao, Dexin Kong, Heng Wu
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied
Autor:
Thomas J. Haigh, Kangguo Cheng, Liying Jiang, James Chingwei Li, Chanro Park, Christopher J. Penny, Don Canaperi, Son V. Nguyen, Sanjay Mehta, Tenko Yamashita
Publikováno v:
ECS Transactions. 85:25-39
Autor:
Vimal Kamineni, Junli Wang, Susan Su Chen Fan, Andre Labonte, Ruilong Xie, Dinesh Gupta, Raja Muthinti, Juntao Li, Dechao Guo, Ryan Kevin J, B. Peethala, Richard Conte, Christopher Prindle, Veeraraghavan S. Basker, Shanti Pancharatnam, Kangguo Cheng, Albert M. Young, Stan D. Tsai, Huiming Bu, H. P. Amanapu, Chanro Park, Balasubramanian S. Haran, Robert R. Robison, Nicolas Loubet, Y. Liang, Huimei Zhou, Kisik Choi, Richard A. Conti, Andreas Knorr, Cave Nigel, Adra Carr, Saraf Iqbal Rashid, Andrew M. Greene, Michael P. Belyansky, Hao Tang, Mark Raymond
Publikováno v:
2019 Symposium on VLSI Technology.
We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both g
Autor:
Kerem Akarvardar, Balasubramanian S. Haran, Dinesh Gupta, Juntao Li, Takashi Ando, Economikos Laertis, James J. Demarest, Andreas Knorr, Kai Zhao, Victor Chan, Ruqiang Bao, Cave Nigel, Huimei Zhou, Richard A. Conti, Veeraraghavan S. Basker, Andrew M. Greene, Huiming Bu, Miaomiao Wang, Robert R. Robison, Kanakasabapathy Sivananda K, Indira Seshadri, Chanro Park, Dechao Guo, Muthumanickam Sankarapandian, Ruilong Xie, Liying Jiang
Publikováno v:
2019 Symposium on VLSI Technology.
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which redu
Publikováno v:
2018 IEEE Nanotechnology Symposium (ANTS).
The impact of oxygen containing plasma treatment on the electrical properties of gate stack is evaluated by measuring the interfacial layer thickness as a function of plasma treatment condition and by characterizing electrical parameters, such as thr
Autor:
Paul S. McLaughlin, Thomas J. Haigh, Devika Sil, Huai Huang, Nicholas A. Lanzillo, Raghuveer R. Patlolla, Pranita Kerber, Hosadurga Shobha, James Chingwei Li, C. B. Pcethala, Yongan Xu, Donald F. Canaperi, James J. Demarest, Elbert E. Huang, Chanro Park, Clevenger Leigh Anne H, Benjamin D. Briggs, Licausi Nicholas, Jae Gon Lee, M. Ali, Son Nguyen, Young-Wug Kim, Theodorus E. Standaert, C. T. Le, G. Lian, Griselda Bonilla, Errol Todd Ryan, Han You, David L. Rath
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating
Autor:
Oleg Gluschenkov, Zuoguang Liu, Chengyu Niu, Andreas Knorr, Tenko Yamashita, Jay W. Strane, Mukesh Khare, Gen Tsutsui, Chris M. Prindle, Abraham Arceo, Indira Seshadri, Bruce Miao, A. Petrescu, Stan D. Tsai, Curtis Durfee, Soon-Cheon Seo, Adra Carr, Jie Yang, Walter Kleemeier, Kisik Choi, F. Lie, W. Wang, Rama Divakaruni, Chanro Park, Mark Raymond, Heng Wu, Huiming Bu, Dechao Guo, Anuja DeSilva, George Yang, Dinesh Gupta, Muthumanickam Sankarapandian, Praneet Adusumilli, Sam Choi, Kerem Akarvardar
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional appr