Zobrazeno 1 - 10
of 60
pro vyhledávání: '"Changku Hwang"'
Autor:
Sebastian Turullols, Ha Pham, Yifan YangGong, Yuanjung David Lin, Hoyeol Cho, Heechoul Park, Dawei Huang, Sudesna Dash, Curtis McAllister, Hongping Penny Li, Changku Hwang, Ali Vahidsafa, Chaoyang Zheng, Vijay Srinivasan, Jeffrey S. Brooks, Francis Schumacher, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Alan P. Smith, Paul N. Loewenstein, Robert P. Masleid, Robert T. Golla
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:79-91
The SPARC M7 processor offers up to 3 $\times$ the throughput performance of Oracle's previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a606e12b1bb30f7903054601615aeadb
https://doi.org/10.1109/jssc.2015.2456902
https://doi.org/10.1109/jssc.2015.2456902
Autor:
King C. Yen, Aparna Ramachandran, Timothy P. Johnson, Yongning Sheng, Jason M. Hart, Daisy Jian, Rakesh Mehta, Yuefei Ge, Dawei Huang, Lance Kwong, Hoyeol Cho, Zuxu Qin, Changku Hwang, Jinuk Luke Shin, Umesh Gajanan Nawathe, Robert P. Masleid, Venkat Krishnaswamy, Georgios Konstadinidis, Hari Sathianathan, Gregory Gruber, Sebastian Turullols
Publikováno v:
ISSCC
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a65bf3aeb8482508a1512e9ba2b864
https://doi.org/10.1109/jssc.2013.2284648
https://doi.org/10.1109/jssc.2013.2284648
Autor:
Changku Hwang, Jinuk Luke Shin, A S Leon, K.W. Tam, Timothy P. Johnson, Dawei Huang, Hongping Li, A. Strong, Francis Schumacher, Bruce Petrick, Ha Pham, A. Smith
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:131-144
This fourth generation UltraSPARC T3 SoC processor implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable up to 512 threads in a 4-w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3cae5c740667a305aa9d7bb337d0927a
https://doi.org/10.1109/jssc.2010.2080491
https://doi.org/10.1109/jssc.2010.2080491
Autor:
Changku Hwang, Paul N. Loewenstein, Penny Li, Hoyeol Cho, Heechoul Park, Sudesna Dash, Francis Schumacher, Jinuk Luke Shin, Yuanjung David Lin, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Robert P. Masleid, Chaoyang Zheng, Curtis McAllister, Vijay Srinivasan, Dawei Huang
Publikováno v:
ISSCC
The SPARC M7 processor delivers more than 3x throughput performance improvement over its predecessor SPARC M6 for commercial applications. It introduces new design features, such as the S4 core, a 64MB L3 cache subsystem with application data integri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::505a30dca4209b053f118f6ef3ee62f4
https://doi.org/10.1109/isscc.2015.7062931
https://doi.org/10.1109/isscc.2015.7062931
Publikováno v:
Analog Integrated Circuits and Signal Processing. 25:347-350
A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \vert {V_{t}}\vert +{2\,V_{ds,sat}} and considerably extends input voltage operating range and achieves high speed operation. As an application exam
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd0a9c17f086d11ace384316d3d6e219
https://doi.org/10.1023/a:1008394318240
https://doi.org/10.1023/a:1008394318240
Publikováno v:
Analog Integrated Circuits and Signal Processing. 19:169-179
In this paper two novel single-ended-input fully-balanced-output circuits (SFC), namely unbuffered and buffered SFCs, are proposed for input interface to fully balanced signal processing systems. The unbuffered SFC overcomes the drawback of uncontrol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::40ee34a5820be4ca09316f49df55527f
https://doi.org/10.1023/a:1008314101118
https://doi.org/10.1023/a:1008314101118
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45:800-811
In this paper, a compact low-power (LP) low-voltage (LV) metal-oxide-semiconductor-only (MOS-only) variable gain amplifier (VCA) is introduced. This amplifier based on complementary MOS (CMOS) transistors operating in strong inversion is composed of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55dab1f8fcc098777500820b15bf7c5a
https://doi.org/10.1109/82.700927
https://doi.org/10.1109/82.700927
Publikováno v:
Analog Integrated Circuits and Signal Processing. 13:261-274
This paper presents two CMOS low-voltage rail-to-rail voltage-to-current converters (V-I converter) which could be used as basic building blocks to construct low-voltage current-mode analog VLSI circuits. In each of the circuits, an N-type V-I conver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4185686a8606d0fc998e2988c6f97a8
https://doi.org/10.1023/a:1008270232673
https://doi.org/10.1023/a:1008270232673
Autor:
J. Hart, S. Butler, null Hoyeol Cho, null Yuefei Ge, G. Gruber, null Dawei Huang, null Changku Hwang, D. Jian, T. Johnson, G. Konstadinidis, L. Kwong, R. Masleid, U. Nawathe, A. Ramachandran, null Yongning Sheng, J. L. Shin, S. Turullois, null Zuxu Qin, null King Yen
Publikováno v:
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d740206905b739c2a7fb6049394c3258
https://doi.org/10.1109/isscc.2013.6487631
https://doi.org/10.1109/isscc.2013.6487631
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:732-739
In this paper we present two on-chip design-for-testability (DFT) schemes for CMOS ICs. One is for small circuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f911f30c7b0520a0db92e938e328b26
https://doi.org/10.1109/4.509857
https://doi.org/10.1109/4.509857