Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Chang-Tzu Lin"'
Autor:
Chang-Tzu Lin, 林昌賜
94
Floorplanning is a critical stage in VLSI (Very Large-Scale Integrated circuits) physical design cycle, for which finding a placement for circuit modules on a chip is important due to high area cost of fabrication. An important factor to the
Floorplanning is a critical stage in VLSI (Very Large-Scale Integrated circuits) physical design cycle, for which finding a placement for circuit modules on a chip is important due to high area cost of fabrication. An important factor to the
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/66563050044563339276
Autor:
Chang, Tzu‐Lin1 (AUTHOR), Wang, Hsiao‐Wen2 (AUTHOR), Lin, Keng‐Pei3 (AUTHOR) kplin@mis.nsysu.edu.tw, Chen, Hsin‐Yu4 (AUTHOR)
Publikováno v:
Managerial & Decision Economics. Oct2022, Vol. 43 Issue 7, p3176-3197. 22p.
Publikováno v:
VLSI-DAT
With the increasing complexity of the design rules, the routability has become one of the most essential factors that should be considered in the placement stage; however, being the routable basis of the placer in the past, the congestion map given b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da7fe46342b883b1c53eaa88985f9f9e
https://doi.org/10.1109/vlsi-dat52063.2021.9427321
https://doi.org/10.1109/vlsi-dat52063.2021.9427321
Akademický článek
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Autor:
Lee I-Hsuan, Wei-Hsun Liao, Chang-Tzu Lin, Ding-Ming Kwai, Chien-Chia Huang, Hung-Ming Chen, Sheng-Hsin Fang, Li-Chin Chen, Yung-Fa Chou
Publikováno v:
ISVLSI
In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/mic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80539180c43a4be867bfb1a8f6a6508f
https://doi.org/10.1109/isvlsi.2017.86
https://doi.org/10.1109/isvlsi.2017.86
Autor:
Wei-Hsun Liao, Yung-Fa Chou, Ding-Ming Kwai, Hung-Ming Chen, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang
Publikováno v:
ASP-DAC
Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9c94137fed703a39d366fe2a2c9c44f
https://doi.org/10.1109/aspdac.2017.7858381
https://doi.org/10.1109/aspdac.2017.7858381
Publikováno v:
ACM Great Lakes Symposium on VLSI
Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::785e6cc7e52c7710adc3ea8514a9d4e4
https://doi.org/10.1145/2902961.2902973
https://doi.org/10.1145/2902961.2902973
Publikováno v:
Engineering Applications of Artificial Intelligence. 20:821-830
Typical floorplanning concerns a series of objectives, such as area, wirelength, and routability, etc., with various aspect ratios of modules in a free-outline regime. However, in a hierarchical design flow for very large ASICs and SoCs, a floorplan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed7c453baee7dade563aae0eb3cb4c16
https://doi.org/10.1016/j.engappai.2006.10.006
https://doi.org/10.1016/j.engappai.2006.10.006
Publikováno v:
Journal of the Chinese Institute of Engineers. 29:383-389
Module floorplanning/placement considering boundary constraints is practical and crucial in modern designs because designers may want to place some I/O involved modules along the chip boundary to minimize both chip area and off‐chip connections. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7c2540734cb78c63e8ae121ba286716
https://doi.org/10.1080/02533839.2006.9671134
https://doi.org/10.1080/02533839.2006.9671134
Publikováno v:
Journal of Circuits, Systems and Computers. 15:107-127
Typical floorplanning problem concerns a series of objectives, such as area, wirelength and routability, etc., without any specific constraint in a free-outline style. Entering SOC era; however, modern floorplanning takes more care of providing extra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6577222432d3b814cede18fa2141dbca
https://doi.org/10.1142/s0218126606002940
https://doi.org/10.1142/s0218126606002940