Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Chang-Lun Lu"'
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
Traditional IC packaging requires chips to be assembled at the same level, while recently thrived 2.5D/3D IC packaging utilizes skyscraper approach to stack various types of chips with diverse functions occupying similarfootprint, and this approach n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d020aacd5d37f9e2fb821be0ed4ecb6
https://doi.org/10.1109/ectc.2017.20
https://doi.org/10.1109/ectc.2017.20
Autor:
Chen Lu-Yi, Chen-Hong Chiu, Chang-Lun Lu, Cheng-Hsiang Liu, Shih-Ching Chen, Hsiao-Chun Huang
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Conventional IC packaging requires chips to be packaged at the same level, while newly developed 2.5D/3D IC packaging utilizes skyscraper approach to stack various types of chips with diverse functions occupying similar footprint, not only reducing o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::299686b769d2cead8246e0675d695c85
https://doi.org/10.1109/ectc.2016.61
https://doi.org/10.1109/ectc.2016.61
Publikováno v:
2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
Latest portable or consumer electronic devices have driven packaging technology and industry towards the direction of 3D IC for vertical interconnection between homogenous or heterogeneous chips integration based on diverse applications. Since 3D IC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26b5245a90d2ab52d0085980213dafc4
https://doi.org/10.1109/ectc.2015.7159797
https://doi.org/10.1109/ectc.2015.7159797
Autor:
Rui-Feng Tai, Chang-Lun Lu, Kenny Liu, Steve Chiu, Hsiao-Chun Huang, Chun-Tang Lin, Hsi-chang Hsu, David Chang, Hong-Da Chang, Yi-Che Lai
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
Wafer Level Packaging (WLP) is a packaging technology focusing on integrated circuit (IC) packaging at wafer level instead of die level. WLP essentially consists of IC foundry fabrication process and subsequent device interconnection and back-end pas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08500fc46f004470ba31b35c3316b9e3
https://doi.org/10.1109/ectc.2014.6897402
https://doi.org/10.1109/ectc.2014.6897402
Autor:
Chun-Chieh Chao, Jyun-Ling Tsai, Hsiao-Chun Huang, Cheng-Hsiang Liu, Hung-Hsien Chang, Chang-Lun Lu, Shih-Ching Chen
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
Interfacial delamination between backside of TSV thin wafer silicon, low temperature PECVD silicon nitride and UBM (under bump metallurgy) layer under room temperature and thermal cycling or processing have been investigated in this paper. FEA (Finit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8cfa61a1ae23dc02f0d173f43e2ba788
https://doi.org/10.1109/ectc.2014.6897388
https://doi.org/10.1109/ectc.2014.6897388
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
Conventional IC packaging requires device chips or dice to be packaged at the same level in a way we generally imagined, while newly developed and thriving 3D IC packaging utilizes skyscraper concept to stack numerous types of device chips with diffe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b10477c5ae388f6e115f14cbdc1825df
https://doi.org/10.1109/ectc.2014.6897513
https://doi.org/10.1109/ectc.2014.6897513