Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Chang-Kyo Lee"'
Autor:
Hyong-Ryol Hwang, Young-Soo Sohn, Young Hoon Son, Seungseob Lee, Seung-Jun Bae, Hyuck-Joon Kwon, Jung-Bae Lee, Byongwook Na, Chang-Kyo Lee, Young-Hwa Kim, Dongkeon Lee, Duk-ha Park, Daesik Moon, Kwang-Il Park, Tae-Young Oh, Youn-sik Park, Kyung-Soo Ha
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:157-166
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM is implemented in a 1 $\times$ nm DRAM process. Various techniques are applied to achieve higher bandwidth and lower power than LPDDR4X. To increase data rate, a WCK clocking scheme that is less vulnerable to power no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3c0d249a308f28f1535a7ab42eb92fc
https://doi.org/10.1109/jssc.2019.2938396
https://doi.org/10.1109/jssc.2019.2938396
Autor:
Seung-Tak Ryu, Chang-Kyo Lee
Publikováno v:
IET Circuits, Devices & Systems. 13:1277-1283
This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12-bit 200 MS/s replica driving pipelined analogue-to-digital converter (ADC). Based on the noise design strategy with the target e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ab406746de3358c0d1f82dbaf33e167
https://doi.org/10.1049/iet-cds.2018.5308
https://doi.org/10.1049/iet-cds.2018.5308
Autor:
Kim Sang-Yun, Junghwan Park, Soo-bong Chang, Won-Il Bae, Ki-Won Park, Hyuck-Joon Kwon, Seung-Jun Bae, Geun-Tae Park, Hyung-Joon Chi, Kyung-Ho Lee, Hye-In Choi, Ji-Suk Kwon, Gil-Young Kang, Seung-Jun Lee, Hyunyoon Cho, Jin-Seok Heo, Young-Soo Sohn, Lim Suk-Hyun, Kyung Ryun Kim, Kwang-Il Park, Daesik Moon, Chang-Kyo Lee, Jae-Hoon Jung, Dongkeon Lee, Chang-Ho Shin, Cheol Kim, Jung-Bae Lee, Young-Il Lim, Dae Hyun Kim, Jinsol Park, Seouk-Kyu Choi, Jin-Hun Jang, Ki-Han Kim, Young Hoon Son, Byongwook Na, Isak Hwang, Duk-ha Park, Su-Yeon Doo, Choi Yeon-Kyu
Publikováno v:
ISSCC
Energy efficiency in mobile devices is a pivotal criteria from the overall system point of view, Although the 7,5Gb/s 8Gb LPDDR5 [1], with low-power schemes (internal data copy, dynamic-voltage-frequency scaling (DVFS), and a deep-sleep mode (DSM)),
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2d3bf8b7cf0e24bdfbbca56a91c30e7
https://doi.org/10.1109/isscc19947.2020.9062914
https://doi.org/10.1109/isscc19947.2020.9062914
Autor:
Jongwook Park, Jung-Hwan Choi, Seung-Jun Bae, Si-Hyeong Cho, Seunseob Lee, Young-Ryeol Choi, In-Dal Song, Kwang-Il Park, Ki-Ho Kim, Jin-Seok Heo, Young-Soo Sohn, Dong-Hun Lee, Eunsung Seo, Junha Lee, Gil-Hoon Cha, Hyuck-Joon Kwon, Jin-Hyeok Baek, Daesik Moon, Youn-sik Park, Kyung-Soo Ha, Chang-Kyo Lee, Seok-Hun Hyun, Seong-Jin Jang
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2906-2916
This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted out
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::357e219db9060554f370c477b6da0d04
https://doi.org/10.1109/jssc.2018.2850937
https://doi.org/10.1109/jssc.2018.2850937
Autor:
Daesik Moon, Jung-Hwan Choi, Seok-Hun Hyun, Jung-Bae Lee, Sung-Woo Yoon, Su-Jin Park, Dong-Hoon Lee, Jin-Hyeok Baek, Seung-Jun Bae, Y.S. Park, Hui-Kap Yang, Ki-Han Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Chang-Kyo Lee, Bok-Gue Park, Young-Jae Kim, Jin-Seok Heo, Kyungryun Kim, Soobong Jang, Ki-Ho Kim, Joung-Wook Moon, Kwang-Il Park, Jae-Hyung Lee
Publikováno v:
VLSI Circuits
A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3570d22e6ced3e4156d6ecfd888ad57d
https://doi.org/10.23919/vlsic.2019.8778102
https://doi.org/10.23919/vlsic.2019.8778102
Autor:
Soo-bong Chang, Young-Soo Sohn, Hyuck-Joon Kwon, Duk-ha Park, Hyong-Ryol Hwang, Junghwan Park, Kwang-II Park, Choi Yeon-Kyu, Young Hoon Son, Hyunyoon Cho, Byongwook Na, Hyung-Joon Chi, Lim Suk-Hyun, Jin-Hun Jang, Tae-Young Oh, Seung-Jun Shin, Seouk-Kyu Choi, Daesik Moon, Kim Sang-Yun, Ki-Won Park, Seong-Jin Jang, Hyo-Joo Ahn, Jung-Hwan Choi, Seungseob Lee, Chang-Kyo Lee, Dongkeon Lee, Young-Hwa Kim, Youn-sik Park, Kyung-Soo Ha, Seok-Hun Hyun
Publikováno v:
ISSCC
High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1–3], have been developed to enable high-resolution displays, multiple cameras and 4G communication in mobile devices. However, DRAM with higher bandwidth and lower
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f8b77e89febd51cb1428fa3986dea1f
https://doi.org/10.1109/isscc.2019.8662509
https://doi.org/10.1109/isscc.2019.8662509
Autor:
Jung-Hwan Choi, In-Dal Song, Jin-Oh Ahn, Kwang-Il Park, Daesik Moon, Dong-Ju Kim, Kyung-Soo Kim, Jin-Seok Heo, Seung-Jun Bae, Seokhong Kwon, Young-Soo Sohn, Jin-Hyeok Baek, Jongmin Kim, Byung-Cheol Kim, Hyuck-Joon Kwon, Chang-Kyo Lee, Seong-Jin Jang, Jeonghyeon Cho, Min-Su Ahn, Jeong-Sik Nam, Ilgweon Kim, Seok-Hun Hyun, Jeong-Hoon Oh, Gil-Hoon Cha, Jae-Joon Song, Ki-Ho Kim
Publikováno v:
VLSI Circuits
A sub-0.85V, 6.4Gb/s TX-interleaved transceiver with fast wake-up time using 2-step charging control and a V OH calibration scheme is implemented using 20nm DRAM process. Adopting an interleaving scheme based on improved DRAM process, the proposed de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d55ad90ea415991e854486a0366baf5f
https://doi.org/10.1109/vlsic.2018.8502299
https://doi.org/10.1109/vlsic.2018.8502299
Autor:
Seung-Jun Bae, Jongwook Park, Young-Soo Sohn, Taesung Kim, Sewon Eom, Young-Seok Kim, Hyuck-Joon Kwon, Daesik Moon, Seong-Hwan Kim, Ki-Ho Kim, Seungseob Lee, Eungsung Seo, Jin-Hyeok Baek, Yoon-Joo Eom, Kyoung-Ho Kim, Jung-Hwan Choi, Tae-Young Oh, Gil-Hoon Cha, Seok-Hun Hyun, Yoon-Gyu Song, Youn-sik Park, Kyung-Soo Ha, Young Hoon Son, Dae-Hee Jung, In-Dal Song, Kwang-Il Park, Hyunyoon Cho, Bo-Tak Lim, Chang-Kyo Lee, Si-Hyeong Cho, Joon-Young Park, Junha Lee, Jin-Seok Heo, Young-Ryeol Choi, Seong-Jin Jang
Publikováno v:
A-SSCC
This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the suppl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49e6cc5f556a1c86f0e956ef3176bfec
https://doi.org/10.1109/asscc.2017.8240239
https://doi.org/10.1109/asscc.2017.8240239
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:6-10
A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given constraints,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed3b2f2fc50983743c8adfee8485c41a
https://doi.org/10.1109/tcsii.2013.2290910
https://doi.org/10.1109/tcsii.2013.2290910
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 60:557-561
This paper proposes a replica-driving technique that can be applied to implement low-power high-performance switched-capacitor (SC) amplifiers. The reduced swing range problem arising from the output-stage source-follower is resolved by a simple SC l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29422e8ca8d5d326662aa2449923521f
https://doi.org/10.1109/tcsii.2013.2268432
https://doi.org/10.1109/tcsii.2013.2268432