Výsledky vyhledávání - "Chang, Kevin K."

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What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

Autor: Ghose, Saugata, Yağlıkçı, Abdullah Giray, Gupta, Raghav, Lee, Donghyuk, Kudrolli, Kais, Liu, William X., Hassan, Hasan, Chang, Kevin K., Chatterjee, Niladrish, Agrawal, Aditya, O'Connor, Mike, Mutlu, Onur

Main memory (DRAM) consumes as much as half of the total system power in a computer today, resulting in a growing need to develop new DRAM architectures and systems that consume less power. Researchers have long relied on DRAM power models that are b

Externí odkaz: http://arxiv.org/abs/1807.05102

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Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency

Autor: Chang, Kevin K., Yaglıkçı, Abdullah Giray, Ghose, Saugata, Agrawal, Aditya, Chatterjee, Niladrish, Kashyap, Abhijith, Lee, Donghyuk, O'Connor, Mike, Hassan, Hasan, Mutlu, Onur

This paper summarizes our work on experimental characterization and analysis of reduced-voltage operation in modern DRAM chips, which was published in SIGMETRICS 2017, and examines the work's significance and future potential. We take a comprehensive

Externí odkaz: http://arxiv.org/abs/1805.03175

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LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency

Autor: Chang, Kevin K., Nair, Prashant J., Ghose, Saugata, Lee, Donghyuk, Qureshi, Moinuddin K., Mutlu, Onur

This paper summarizes the idea of Low-Cost Interlinked Subarrays (LISA), which was published in HPCA 2016, and examines the work's significance and future potential. Contemporary systems perform bulk data movement movement inefficiently, by transferr

Externí odkaz: http://arxiv.org/abs/1805.03184

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Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips

Autor: Chang, Kevin K., Kashyap, Abhijith, Hassan, Hasan, Ghose, Saugata, Hsieh, Kevin, Lee, Donghyuk, Li, Tianshi, Pekhimenko, Gennady, Khan, Samira, Mutlu, Onur

This article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which was published in SIGMETRICS 2016, and examines the work's significance a

Externí odkaz: http://arxiv.org/abs/1805.03154

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Understanding and Improving the Latency of DRAM-Based Memory Systems

Autor: Chang, Kevin K.

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memor

Externí odkaz: http://arxiv.org/abs/1712.08304

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Improving DRAM Performance by Parallelizing Refreshes with Accesses

Autor: Chang, Kevin K., Lee, Donghyuk, Chishti, Zeshan, Alameldeen, Alaa R., Wilkerson, Chris, Kim, Yoongu, Mutlu, Onur

Publikováno v: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), Orlando, FL, 2014, pp. 356-367

Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR DRAM refreshes cells at the rank level. This degrades performance significantly because it prevents an entire rank from serving memory requests while bein

Externí odkaz: http://arxiv.org/abs/1712.07754

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Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms

Autor: Chang, Kevin K., Yağlıkçı, Abdullah Giray, Ghose, Saugata, Agrawal, Aditya, Chatterjee, Niladrish, Kashyap, Abhijith, Lee, Donghyuk, O'Connor, Mike, Hassan, Hasan, Mutlu, Onur

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consum

Externí odkaz: http://arxiv.org/abs/1705.10292

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Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism

Autor: Chang, Kevin K., Loh, Gabriel H., Thottethodi, Mithuna, Eckert, Yasuko, O'Connor, Mike, Manne, Srilatha, Hsu, Lisa, Subramanian, Lavanya, Mutlu, Onur

Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can productively utilize this much cache space, however. Unfortunately, the unu

Externí odkaz: http://arxiv.org/abs/1602.00722

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