Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Chanemougame, Daniel"'
Thèse doctorat : Dispositifs de l'Electronique Intégrée : Villeurbanne, INSA : 2005.
Contient 1 glossaire. Titre provenant de l'écran-titre. Bibliogr. p. 210-223.
Contient 1 glossaire. Titre provenant de l'écran-titre. Bibliogr. p. 210-223.
Externí odkaz:
http://docinsa.insa-lyon.fr/these/pont.php?id=chanemougame
Publikováno v:
2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
New tools and methodologies are fused with conventional elements of the process-design-kit (PDK) and design enablement to introduce a rigorous yet fast and agile technology prototyping platform. This design technology cooptimization (DTCO) solution r
Autor:
Subhadeep Kal, Karine Kenis, Trace Hurd, Yusuke Muraki, Peter Biolsi, Cheryl Alix, Aelan Mosden, Naoto Horiguchi, Yusuke Oniki, Frank Holsteyns, Kaushik A. Kumar, Efrain Altamirano-Sánchez, Chanemougame Daniel
Publikováno v:
Advanced Etch Technology for Nanopatterning IX.
R&D on transistor fabrication and scaling for current and future technology nodes involves various 3D-device architectures like the established finFET (fin “Field Effect Transistor”), and newer architectures like GAA (Gate All Around) which may i
Autor:
Chanemougame Daniel, Jonathan Cobb, Chia-Tung Ho, Lars W. Liebmann, Jeffrey Smith, Victor Moroz, Pete Churchill
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIV.
An efficient Pathfinding DTCO analysis flow which allows rapid block-level power, performance, and area (PPA) characterization is presented. To optimize this flow for the exploration of innovative technology-architecture definitions, i.e. new devices
Autor:
Andrew M. Greene, Aelan Mosden, Peter Biolsi, Cheryl Alix, Jeffrey Smith, Veeraraghavan S. Basker, Subhadeep Kal, Daniel Schmidt, Michael P. Belyansky, Koji Watanabe, Frougier Julien, Shanti Pancharatnam, Nicolas Loubet, Jingyun Zhang, Flaugh Matthew, Dechao Guo, Kai Zhao, Huimei Zhou, Maruf Bhuiyan, Balasubramanian S. Haran, Chanemougame Daniel, Miaomiao Wang, Curtis Durfee, Huiming Bu, Ivo Otto, Mary Breton
Publikováno v:
ECS Meeting Abstracts. :943-943
Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applic
Autor:
R. Divakaruni, C. Alix, Trace Hurd, M. Sankar, Aelan Mosden, Mary Breton, Thamarai S. Devarajan, Huimei Zhou, Chanemougame Daniel, Shanti Pancharatnam, Peter Biolsi, Subhadeep Kal, Andrew M. Greene, V. Basker, Kandabara Tapily, Jeffrey Smith, Balasubramanian S. Pranatharthi Haran, Jingyun Zhang, N. Haller, Michael P. Belyansky, Curtis Durfee, Robin Chao, Huiming Bu, Koji Watanabe, Xin Miao, Lan Yu, Frougier Julien, Nicolas Loubet
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
In this paper, we demonstrate a first of a kind SiGe dry etch technique for the formation of inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around device architectures. This novel etch involves a precisely controlled
Autor:
V. Gerousis, N. Nakamoto, Chanemougame Daniel, Lars W. Liebmann, K. Sun, Gregory A. Northrop, M. Facchini, Z. Baum, L. Riviere Cazaux, Han Geng
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XII.
This paper describes a rigorous yet flexible standard cell place-and-route flow that is used to quantify block-level power, performance, and area trade-offs driven by two unique cell architectures and their associated design rule differences. The two
Autor:
M. Celik, Michel Haond, R. Sampson, S. Kanakasabapathy, Balasubramanian S. Pranatharthi Haran, L. Grenouillet, Scott Luning, T. Skotnicki, Walter Kleemeier, Pierre Morin, Shom Ponoth, S. Guillaumet, Chanemougame Daniel, R. Johnson, J. L. Bataillon, T. Levin, Olivier Weber, Ali Khakifirooz, James Chingwei Li, Romain Wacquez, H. Kothari, Gen Tsutsui, Frederic Allibert, Lisa F. Edge, Kangguo Cheng, Mukesh Khare, Swati Mehta, Nicolas Loubet, Emmanuel Josse, M. Vinet, Huiming Bu, F. Chafik, J. Gimbert, Toshiharu Nagumo, Y. Le Tiec, Qing Liu, Bruce B. Doris, O. Faynot, J. Kuss
Publikováno v:
2013 IEEE International Electron Devices Meeting.
We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET).
Autor:
Han, Jin-Ping, Shimizu, Takashi, Pan, Li-Hong, Voelker, Moritz, Bernicot, Christophe, Arnaud, Franck, Mocuta, Anda, Stahrenberg, Knut, Azuma, Atsushi, Eller, Manfred, Yang, Guoyong, Jaeger, Daniel, Zhuang, Haoren, Miyashita, Katsura, Stein, Kenneth, Nair, Deleep, Park, Jae Hoo, Kohler, Sabrina, Hamaguchi, Masafumi, Li, Weipeng, Kim, Kisang, Chanemougame, Daniel, Kim, Nam Sung, Uchimura, Sadaharu, Tsutsui, Gen, Wiedholz, Christian, Miyake, Shinich, Meer, Hans van, Liang, Jewel, Ostermayr, Martin, Lian, Jenny, Celik, Muhsin, Donaton, Ricardo, Barla, Kathy, Na, MyungHee, Goto, Yoshiro, Sherony, Melanie, Johnson, Frank S., Wachnik, Richard, Sudijono, John, Kaste, Ed, Sampson, Ron, Ku, Ja-Hum, Steegen, An, Neumueller, Walter
Publikováno v:
Japanese Journal of Applied Physics; April 2011, Vol. 50 Issue: 4 p04DC13-04DC15, 3p