Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Chandramouli Kashyap"'
Publikováno v:
DAC
Analog circuit sizing takes a significant amount of manual effort in a typical design cycle. With rapidly developing technology and tight schedules, bringing automated solutions for sizing has attracted great attention. This paper presents DNN-Opt, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ec2dd3ad938349eac18effa824ac56b1
https://eprints.gla.ac.uk/252778/2/252778.pdf
https://eprints.gla.ac.uk/252778/2/252778.pdf
Publikováno v:
DAC
A novel machine learning based parasitic estimation (MLParest) method for pre-layout custom circuit design is presented. It reduces the error between pre-layout and post-layout circuit simulation from 37% to 8% on average for different measurements a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbf7c01a50e85a7097d1a09ae1c123a3
https://doi.org/10.1109/dac18072.2020.9218495
https://doi.org/10.1109/dac18072.2020.9218495
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:466-478
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been proposed, the results are often pessimistic with many false failures. We
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f07002b84ca51382dee9644802fa7d2f
https://doi.org/10.1109/tcad.2009.2035532
https://doi.org/10.1109/tcad.2009.2035532
Publikováno v:
IEEE Design & Test. 33:5-6
The articles in this special section focus on analog-mix-signal CAD design. With the advent of "Internet of Things" always connected, sensor-driven electronics are becoming a pervasive part of our lives. Fueled by the commoditization of digital compu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c201384f9ab0dadadc504d4cefc5a66
https://doi.org/10.1109/mdat.2016.2594182
https://doi.org/10.1109/mdat.2016.2594182
Autor:
Chandramouli Kashyap
Publikováno v:
Proceedings of the 47th Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93c5cb2ee66fd36a68a663ae55b22b70
https://doi.org/10.1145/3254444
https://doi.org/10.1145/3254444
Publikováno v:
ICCAD
Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has been aimed at handling parameter variations as part of timing analysi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::979db53bee52baa1cbcc122ecef78831
https://doi.org/10.1145/1687399.1687438
https://doi.org/10.1145/1687399.1687438
Publikováno v:
DAC
Empirically characterized equation- and table-based cell models have been applied in static timing analysis for decades. These models have been extended to handle a variety of environmental and circuit phenomena over the years. This has given rise to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c0596e804086bbc28b886df64e7fcf1
https://doi.org/10.1145/1391469.1391589
https://doi.org/10.1145/1391469.1391589
Publikováno v:
DAC
Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitivities of the timing slacks to parameter variations. This additional slack
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50c76af108ce979b917a1cd38de448b7
https://doi.org/10.1145/1391469.1391647
https://doi.org/10.1145/1391469.1391647
Publikováno v:
DAC
Timing, test, reliability, and noise are modeled and abstracted in our design and verification flows. Specific EDA algorithms are then designed to work with these abstracted models, often in isolation of other effects. However, tighter design margins
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7096d2d8a9c39bc80d4d3fa7da499c9d
https://doi.org/10.1109/dac.2007.375194
https://doi.org/10.1109/dac.2007.375194
Publikováno v:
DAC
The problem of multiple-input switching (MIS) has been mostly ignored by the timing CAD community. Not modeling MIS for timing can result in as much as 100% error in stage delay and slew calculation. The impact is especially severe on stages immediat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7691cadc0755a3aad7be3ac94b982df4
https://doi.org/10.1145/1146909.1146974
https://doi.org/10.1145/1146909.1146974