Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Chandarasekaran Ramamurthy"'
Autor:
Chen Sun, Chen Li, Derek Van Orden, Behrooz Beheshtian, Chong Zhang, Pavan Bhargava, Haiwei Lu, Daniel Jeong, Michael Rust, Mason Zhang, Forrest Sedgwick, Woorham Bae, Shahab Ardalan, Chandarasekaran Ramamurthy, Mark T. Wade, Roy Meade, Erik Anderson, Sidney Buchbinder, Austin Katzin, John M. Fini, Anatoly Khilo, Vladimir Stojanovic, Byungchae Kim
Publikováno v:
VLSI Circuits
For the first time, we demonstrate an error-free, 128Gbps (8x16Gbps) optical transceiver using a microring-based wavelength-division multiplexed (WDM) architecture. The optical transceiver ran for 12 hours with zero errors, resulting in a measured bi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d7c5203a9db0d2ef9c73760b17560ce
https://doi.org/10.23919/vlsicircuits52068.2021.9492382
https://doi.org/10.23919/vlsicircuits52068.2021.9492382
Autor:
M. Patel, C. Madden, J. Frey, U. Krishnamoorthy, Michael Rust, Pavan Bhargava, N. Chan, Songtao Liu, R. Roucka, Forrest Sedgwick, Mark T. Wade, H. Eachempatti, Austin Katzin, Erik Anderson, F. Luna, Sidney Buchbinder, Chen Li, D. Van Orden, John M. Fini, M. Sysak, Manan Raval, L. Okada, Mason Zhang, Chandarasekaran Ramamurthy, Shahab Ardalan, Chong Zhang, Anatoly Khilo, Haiwei Lu, R. Zeng, Woorham Bae, Derek M. Kita, K. Robberson, E. Jan, Behrooz Beheshtian, P. Chao, Roy Meade, Daniel Jeong, K. Chang, Vladimir Stojanovic, Byungchae Kim, Chen Sun
Publikováno v:
OFC
We demonstrate 128 Gbps/port (8-λ × 16 Gbps/λ) natively error-free transmission across eight optical ports using a 8-port, 8-λ/port WDM remote laser source and a pair of monolithically integrated CMOS optical I/O chiplets with 4.96-5.56 pJ/bit op
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f89c95579e1894371143e1d5a8686f12
https://doi.org/10.1364/ofc.2021.f3c.6
https://doi.org/10.1364/ofc.2021.f3c.6
Autor:
Chong Zhang, Haiwei Lu, Woorham Bae, Mark T. Wade, Forrest Sedgwick, Pavan Bhargava, Erik Anderson, Sidney Buchbinder, Chen Li, Mason Zhang, Derek Van Orden, Vladimir Stojanovic, Shahab Ardalan, Michael Rust, Roy Meade, Behrooz Beheshtian, Chandarasekaran Ramamurthy, Chen Sun, Daniel Jeong, Austin Katzin, John M. Fini, Anatoly Khilo
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The $5.5\mathrm{x}8.9\mathrm{mm}^{2}$ chiplet uses the Advanced Interface Bus (AIB), a parallel digital interface, to communicate to a host ASIC and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::375b924c1bef7e11c732a46677a6b9e2
https://doi.org/10.1109/vlsitechnology18217.2020.9265012
https://doi.org/10.1109/vlsitechnology18217.2020.9265012
Autor:
Lawrence T. Clark, Vinay Vashishtha, Aditya Gujja, Chandarasekaran Ramamurthy, Saurabh Sinha, Greg Yeric, Brian Cline, Lucian Shifren
Publikováno v:
Microelectronics Journal. 53:105-115
We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3b6a8af63b40d542a074454a9de5f9dc
Publikováno v:
IEEE Transactions on Computers. 65:382-395
A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17a826b8d081448ff9a2c52e8e2c0165
https://doi.org/10.1109/tc.2015.2419661
https://doi.org/10.1109/tc.2015.2419661
Autor:
Srivatsan Chellappa, Vinay Vashishtha, Chandarasekaran Ramamurthy, Anudeep R. Gogulamudi, Lawrence T. Clark
Publikováno v:
IEEE Transactions on Nuclear Science. 62:3040-3048
The use of pulse-clocked latches has become ubiquitous in commercial unhardened integrated circuits (ICs) both for their performance and power benefits. In this paper, their use in soft-error hardened triple modular redundant (TMR) circuits is presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::101333ea60bc5150e28d5f87a1c09486
https://doi.org/10.1109/tns.2015.2498919
https://doi.org/10.1109/tns.2015.2498919
Publikováno v:
2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS).
This abstract proposes a novel radiation hardened all-digital multiplying delay locked loop. The design uses pulse-clocking to create a high frequency clock for use in DDR2 and DDR3 data recovery and transmit without intermediate frequency generation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55b6358fc3ddf292dc7edef78e0ef10b
https://doi.org/10.1109/radecs.2017.8696144
https://doi.org/10.1109/radecs.2017.8696144
Autor:
Vinay Vashishtha, Chandarasekaran Ramamurthy, Srivatsan Chellappa, Aditya Gujja, Lawrence T. Clark
Publikováno v:
2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS).
This work describes voting feedback circuits for triple modular redundant (TMR) self-correcting flip-flops that reduce the flip-flop circuit area by 20% and the energy consumption by 10% over the conventional use of a majority gate. A fully pipelined
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5aaac6fe84640e80d7387f4eaaa66f56
https://doi.org/10.1109/radecs.2017.8696212
https://doi.org/10.1109/radecs.2017.8696212
Publikováno v:
SPIE Proceedings.
Line and cut based patterning for BEOL layers is an attractive solution to address the block mask patterning challenges related to self-aligned double patterning. It also enables integrated fill, with fill as an artifact of unused metal routes follow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6674bc9bad72edeb8c409887b292672b
https://doi.org/10.1117/12.2258085
https://doi.org/10.1117/12.2258085
Publikováno v:
2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS).
An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both SEU and SET with reduced power consumption. The approach utilizes commercial CAD tools. An advanced encryption system is implemented with the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8f5bfff35bdefbc7decf68a222f8c3e
https://doi.org/10.1109/radecs.2015.7365658
https://doi.org/10.1109/radecs.2015.7365658