Zobrazeno 1 - 8
of 8
pro vyhledávání: '"ChanHa Hwang"'
Publikováno v:
Model Assisted Statistics and Applications. 15:239-248
Spatial panel data model captures spatial interactions across spatial units and over time. Lots of effort have been devoted to develop effective estimation methods for parametric and nonparametric spatial panel data models. Varying coefficient model
Autor:
MinJae Lee, Sungsoon Park, Myung-June (M J) Lee, Youshin Jung, Choonheung Lee, DongSu Ryu, Yanggyoo Jung, ChanHa Hwang, Sunwoo Park, Miguel Jimarez
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pi
Autor:
SeungJae Lee, BooYang Jung, Kicheol Bae, Choonheung Lee, Jiheon Yu, YoungSuk Chung, SangWon Kim, Brett Arnold Dunlap, Nozad Karim, Jin Young Kim, ChanHa Hwang
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-
Publikováno v:
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS).
This paper discuss electrical characterization of new developed hybrid package, FusionQuad, that is converging QFN and TQFP type package to have good electrical performance with high I/O pin counts. Precise electrical modelling from wire-to-motherboa
Autor:
Do Hyung Kim, KyeongSool Seong, ChoonHeong Lee, BongChan Kim, Yoon-joo Kim, JaeKyu Song, ChanHa Hwang
Publikováno v:
2009 59th Electronic Components and Technology Conference.
In the semiconductor market, the trend of packaging for die stacking technology moves to high density with thinner chips and higher capacity of memory devices. Moreover, the wafer sawing process is becoming more important for thin wafer, because its
Publikováno v:
2009 59th Electronic Components and Technology Conference.
The current standard for flipchip encapsulantion is a two step process. Following flipchip attach, a liquid underfill material is dispensed along the die edge and allowed to flow, via adhesive capillary force, through the gap between the flipchip die
Autor:
DoHyung Kim, YoonJoo Kim, KyeongSool Seong, JaeKyu Song, BongChan Kim, ChanHa Hwang, ChoonHeong Lee
Publikováno v:
2009 59th Electronic Components & Technology Conference; 2009, p1531-1536, 6p
Publikováno v:
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS); 2009, p1-4, 4p