Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Chan-Kyoung Kim"'
Autor:
Young-Soo Sohn, Gyung-Su Byun, Jung-Hwan Choi, Dong-Jin Lee, Jun-Wan Chai, Soo-In Cho, Jae-Hyoung Lee, Jung Sunwoo, Hoon Lee, Kyu-hyoun Kim, Chan-Kyoung Kim, Chang-Hyun Kim
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A 20-Gb/s 256-Mb DRAM with the proposed PLL and transmitter schemes has been designed and fabricated using an 80-nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with cascaded pre-emphasis transmitte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5d0d96745ea603c63e53c9daa4d9edeb
https://doi.org/10.1109/isscc.2005.1494073
https://doi.org/10.1109/isscc.2005.1494073
Autor:
In-Soo Park, Soo-In Cho, Chan-Kyoung Kim, Jae-Hyung Lee, Won-Ki Park, Uk-Song Kang, Young-Soo Sohn, Hong-Sun Hwang, Byung-Chul Kim, Chang-Hyun Kim, Gyung-Su Byun, Jung-Hwan Choi
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps /spl times/ 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To incr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::312c34fe6abccab2ae5aa623105e933a
https://doi.org/10.1109/vlsic.2005.1469331
https://doi.org/10.1109/vlsic.2005.1469331
Autor:
Soo-In Cho, Dae-Woon Kang, Chang-Hyun Kim, Won-Ki Park, Chan-Kyoung Kim, Young-Soo Sohn, Gyung-Su Byun, In-Young Chung, Jung-Hwan Choi, Hong-Sun Hwang, In-Soo Park, Hoe-ju Chung
Publikováno v:
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0691f562fe75edf0e3a52f57b9c0c280
https://doi.org/10.1109/vlsic.2004.1346493
https://doi.org/10.1109/vlsic.2004.1346493
Autor:
Kyu-hyoun Kim, Young-soo Sohn, Chan-kyoung Kim, Moonsook Park, Dong-jin Lee, Woo-seop Kim, Changhyun Kim
Publikováno v:
IEEE Journal of Solid-State Circuits; Jan2006, Vol. 41 Issue 1, p127-134, 8p, 1 Black and White Photograph, 14 Diagrams, 3 Charts, 2 Graphs
Autor:
Jung-Hwan Choi, Young-Soo Sohn, Chan-Kyoung Kim, Won-Ki Park, Jae-Hyung Lee, Uksong Kang, Gyung-Su Byun, In-Soo Park, Byung-Chul Kim, Hong-Sun Hwang, Chang-Hyun Kim, Soo-In Cho
Publikováno v:
2005 Digest of Technical Papers. 2005 Symposium on VLSI Circuits; 2005, p50-51, 2p
Autor:
Young-Soo Sohn, Jung-Hwan Choi, In-Young Chung, HoeJu Chung, Chan-Kyoung Kim, Gyoung-Su Byun, Dae-Woon Kang, Won-Ki Park, In-Soo Park, Hong-Sun Hwang, Chang-Hyun Kim, Soo-In Cho
Publikováno v:
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525); 2004, p36-37, 2p
Autor:
Kyu-Hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Dong-Jin Lee, Gyung-Su Byun, Hoon Lee, Jae-Hyoung Lee, Jung Sunwoo, Jung-Hwan Choi, Jun-Wan Chai, Changhyun Kim, Soo-In Cho
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005; 2005, p470-470, 1p