Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Cedric Marchand"'
Autor:
Sara Mannaa, Arnaud Poittevin, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Ian O'Connor, Chhandak Mukherjee, Yifan Wang, Houssem Rezgui, Marina Deng, Cristell Maneux, Jonas Muller, Sylvain Pelloquin, Konstantinos Moustakas, Guilhem Larrieu
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 9, Iss 2, Pp 116-123 (2023)
This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphy
Externí odkaz:
https://doaj.org/article/880ac103a0f9440c8b6edc36da7ba0ce
Autor:
Cedric Marchand, Ian O'Connor, Mayeul Cantan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 8, Iss 1, Pp 19-26 (2022)
Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology i
Externí odkaz:
https://doaj.org/article/532a57c5c39f4a34bd00c6e5b5cbaef4
Autor:
Cedric Marchand, Emmanuel Boutillon, Ali Chamas Al Ghouwayel, Hassan Harb, Laura Conde-Canencia
Publikováno v:
SiPS
IEEE Workshop on Signal Processing Systems (SiPS'2021)
IEEE Workshop on Signal Processing Systems (SiPS'2021), Oct 2021, combria, Portugal
IEEE Workshop on Signal Processing Systems (SiPS'2021)
IEEE Workshop on Signal Processing Systems (SiPS'2021), Oct 2021, combria, Portugal
International audience; In this paper, a novel and innovative approach to implement the check node and variable node phases of the EMS algorithm is proposed. The novelty is not only from the hardware side, but also from the algorithmic point of view.
Publikováno v:
IEEE 11th International Symposium on Topics in Coding (ISTC 2021)
IEEE 11th International Symposium on Topics in Coding (ISTC 2021), Aug 2021, Montréal, Canada
ISTC
IEEE 11th International Symposium on Topics in Coding (ISTC 2021), Aug 2021, Montréal, Canada
ISTC
International audience; This paper presents a different vision of the Non-Binary LDPC decoding algorithm. So far, state-of-the-art decoders are mainly focused on the reduction of the check node processing complexity, with a potential side effect on t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5d86e879f6ab6d28e70e9274b10616f2
https://hal.archives-ouvertes.fr/hal-03331821
https://hal.archives-ouvertes.fr/hal-03331821
Autor:
Cedric Marchand, Emmanuel Boutillon
Publikováno v:
ISTC
IEEE 11th International Symposium on Topics in Coding
IEEE 11th International Symposium on Topics in Coding, Aug 2021, Montreal, Canada
IEEE 11th International Symposium on Topics in Coding
IEEE 11th International Symposium on Topics in Coding, Aug 2021, Montreal, Canada
International audience; In most communication systems, the coding rate of the error control code adapts to the channel condition. In this paper, we propose a new approach. A fixed coding rate GF(q) Non-binary code is used as an outer code, and a card
Autor:
Thomas Mikolajick, Evelyn T. Breyer, Stefan Slesazeck, Mayeul Cantan, Ian O'Connor, Cedric Marchand
Publikováno v:
2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-6, ⟨10.1109/DTIS53253.2021.9505078⟩
DTIS
2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-6, ⟨10.1109/DTIS53253.2021.9505078⟩
DTIS
International audience; Emerging non-volatile memories are getting new interest in the system design community. They are used to design logic-in-memory circuits and propose alternatives to von-Neuman architectures. Hafnium oxide-based based ferroelec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::937cbe7589667ea6e9ea4214c916c607
https://hal.archives-ouvertes.fr/hal-03323883
https://hal.archives-ouvertes.fr/hal-03323883
Autor:
Alberto Bosio, Cedric Marchand, Arnaud Poittevin, Ian O'Connor, Mayeul Cantan, Marcello Traiola, Petr Fiser
Publikováno v:
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
DDECS
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
DDECS
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior is turned into a design implementation in terms of logic gates. Historically, logic synthesis was tightly related to the physical imp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fddc660b86bd4de636c459cfba29a5ad
https://hal.archives-ouvertes.fr/hal-03266914
https://hal.archives-ouvertes.fr/hal-03266914
Autor:
Cedric Marchand, Laura Conde-Canencia, Emmanuel Boutillon, Hassan Harb, Ali Chamas Al Ghouwayel
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2019, 66 (2), pp.869-880. ⟨10.1109/TCSI.2018.2866882⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2019, 66 (2), pp.869-880. ⟨10.1109/TCSI.2018.2866882⟩
This paper proposes a unified framework to describe the check node architectures of non-binary low-density parity-check (NB-LDPC) decoders. Forward–backward, syndrome-based, and pre-sorting approaches are first described. Then, they are hybridized
Autor:
Chhandak Mukherjee, Aurélie Lecestre, Cedric Marchand, Sébastien Le Beux, Ian O'Connor, Cristell Maneux, Marina Deng, Guilhem Larrieu, Abhishek Kumar, Arnaud Poittevin, François Marc
Publikováno v:
2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. ⟨10.1109/VLSI-SOC46417.2020.9344094⟩
VLSI-SoC: Design Trends
VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
VLSI-SoC (Selected Papers)
VLSI-SoC: Design Trends ISBN: 9783030816407
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. ⟨10.1109/VLSI-SOC46417.2020.9344094⟩
VLSI-SoC: Design Trends
VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
VLSI-SoC (Selected Papers)
VLSI-SoC: Design Trends ISBN: 9783030816407
International audience; Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawb
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e0334de8c9867a5cb9ad36adf512540
https://hal.science/hal-03166674
https://hal.science/hal-03166674