Zobrazeno 1 - 10
of 52
pro vyhledávání: '"Cathryn Christiansen"'
Autor:
SangHoon Shin, Muhammad A. Alam, Haojun Zhang, Cathryn Christiansen, Patrick Justison, Woojin Ahn, Tian Shen
Publikováno v:
IEEE Transactions on Electron Devices. 64:3555-3562
Spatially resolved precise prediction of local temperature ${T}(\textit {x,y,z})$ is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::877994f590a8b1e7de571cde9f796744
https://doi.org/10.1109/ted.2017.2725742
https://doi.org/10.1109/ted.2017.2725742
Autor:
Haojun Zhang, Tian Shen, Ronald G. Filippi, Linjun Cao, Bianzhu Fu, Kong Boon Yeap, Seungman Choi, Cathryn Christiansen, Patrick Justison, James Zhang, Sean P. Ogden
Publikováno v:
IRPS
Electromigration reliability of BEOL Cu interconnects with various metal line widths and via sizes has been studied. EM lifetime significantly improves from minimum width to three times the minimum width, and then saturates. In addition, the EM lifet
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f339b2b92ceef48dc5396572ea2db08f
https://doi.org/10.1109/irps.2018.8353600
https://doi.org/10.1109/irps.2018.8353600
Autor:
Jeffrey B. Johnson, S. Furkay, Andreas Kerber, Haojun Zhang, N. Rao Mavilla, P. Paliwoda, Prashanth Paramahans Manik, Cathryn Christiansen, E. Maciejewski, Y. Deng, E. Cruz Silva, Shreesh Narasimha, S. Pinkett, Z. Chbili, Mohit Bajaj, Dhruv Singh, C-H. Lin, Oscar D. Restrepo, Srikanth Samavedam
Publikováno v:
IRPS
We present a hierarchical methodology using a combination of ab-initio phonon scattering, electron transmission, and multi-scale finite element simulations to accurately model process specific material physics and component level self-heating in FinF
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16730ee4bb20c832286d5b2b76fdb896
https://doi.org/10.1109/irps.2018.8353650
https://doi.org/10.1109/irps.2018.8353650
Publikováno v:
IRPS
Non-Poisson area scaling behavior has long been observed in BEOL (Back End Of Line) and MOL (Middle Of Line) Time-dependent dielectric breakdown (TDDB) reliability tests due to known variations across the wafer. Three different statistical models hav
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::235aa87a115b0b86631fa0ff54cb40ab
https://doi.org/10.1109/irps.2018.8353661
https://doi.org/10.1109/irps.2018.8353661
Publikováno v:
IRPS
Voltage drop (IR drop) and Electromigration (EM) reliability are two key related aspects for on-chip power grid design considerations. Good EM reliability ensures no EM induced void formation in the interconnect to cause a fatal resistance increase d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4729183cc4d094ddd859dc9ae9c10e95
https://doi.org/10.1109/irps.2018.8353599
https://doi.org/10.1109/irps.2018.8353599
Autor:
Dhruv Singh, A. Gassaria, V. Chauhan, A. da Silva, P. Lindo, Daniel J. Dechene, M. Gribelyuk, I. Ahsan, M. Hasan, Judson R. Holt, Rod Augur, Jaeger Daniel, G. Northrop, G. Gomba, Ghosh Somnath, H. Narisetty, Basanth Jagannathan, Ting-Hsiang Hung, P. Liu, Y. Zhong, T. Gordon, Y. Fan, C. Schiller, A. Blauberg, O. Patterson, B. Morganfeld, Andres Bryant, J. Choo, T. Nigam, B. Senapati, V. Sardesai, N. Baliga, C. An, I. Ramirez, Rishikesh Krishnan, Arkadiusz Malinowski, S. Lucarini, Z. Sun, Sadanand V. Deshpande, R. Bhelkar, Mahender Kumar, Kong Boon Yeap, D. Conklin, Q. Fang, R. Gauthier, Purushothaman Srinivasan, S. Crown, M. Ozbek, Linjun Cao, G. Han, Z. Song, L. Huang, C. Serrau, R. Sweeney, M. Tan, Keith Donegan, Souvick Mitra, A. Zainuddin, P. Agnello, Balasubramanian S. Haran, Haifeng Sheng, B. Greene, A. Hassan, Tabakman Keith, Xin Wang, Sanjay Parihar, L. Cheng, M. Lagus, Jessica Dechene, D. Xu, G. Gifford, M. Zhao, Jeyaraj Antony Johnson, Y. Yan, Rick Carter, Manoj Joshi, W. Kim, Gabriela Dilliway, Jack M. Higman, S. Kalaga, Kai Zhao, Jinping Liu, A. Ogino, M. Lipinski, Amanda L. Tessier, Garo Jacques Derderian, S. Madisetti, N. Shah, Christopher Ordonio, M. Aminpur, Rakesh Ranjan, S. Saudari, Christa Montgomery, Tony Tae-Hyoung Kim, Jeric Sarad, Jae Gon Lee, Bharat Krishnan, Joseph F. Shepard, L. Hu, J. Sporre, Akil K. Sutton, Eswar Ramanathan, Cathryn Christiansen, J.H. Han, J. Lemon, Patrick Justison, Natalia Borjemscaia, Scott C. Johnson, B. Cohen, Kan Zhang, Srikanth Samavedam, G. Xu, T. Xuan, Unoh Kwon, C. Meng, Katsunori Onishi, Y. Shi, C. Huang, R. Coleman, Manfred Eller, Shreesh Narasimha, B. Kannan, J. Yang, Vivek Joshi, W. Ma, Christopher D. Sheraw, A. K. M. Mahalingam, Craig Child, E. Woodard, Tao Chu, Y. Jin, D. K. Sohn, Hasan M. Nayfeh, Mary Claire Silvestre, M. Lingalugari, G. Biery, Tian Shen, Carl J. Radens, E. Kaste, C-H. Lin, K. Han, K. Anil, Ankur Arya, Mehta Jaladhi, Jia Zeng, S.L. Liew, Michael V. Aquilino, M. Yu, M. Chen, Rohit Pal, E. Maciejewski, Stephan Grunow, Robert Fox, Rinus T. P. Lee
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5545f519d7dcbb19a8a64d95e77053fd
https://doi.org/10.1109/iedm.2017.8268476
https://doi.org/10.1109/iedm.2017.8268476
Autor:
Samuel Choi, Minseok Oh, Yan Yan, Anita Madan, Brian A. Cohen, Siddarth A. Krishnan, Andrew H. Simon, Joyeeta Nag, Atsushi Ogino, Baozhen Li, Cathryn Christiansen, Patrick W. DeHaven, Andrew Kim, Jim Shih-Chun Liang
Publikováno v:
ECS Transactions. 69:161-169
We report on an alternative, atomic layer deposited (ALD) TaN barrier scheme for Cu interconnects for 14nm technology node and beyond, i.e., 64nm pitch and/or smaller interconnects. With VLSI integration requiring denser packing of interconnects, con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cb5c8a7ff05cf2dd27c90e2461246bd0
https://doi.org/10.1149/06907.0161ecst
https://doi.org/10.1149/06907.0161ecst
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
Recently a BEOL (Back End Of Line) and MOL (Middle Of Line) Time-dependent dielectric breakdown (TDDB) reliability test and fail rate projection methodology based on large data analysis was proposed and studied. However the extraction of one of the k
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7d3adfb835f18abce2f05522596ee18
https://doi.org/10.1109/irps.2017.7936359
https://doi.org/10.1109/irps.2017.7936359
Publikováno v:
Microelectronics Reliability. 54:712-724
As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d11f946fe83a00f73c66a7c39c59a8a
https://doi.org/10.1016/j.microrel.2014.01.005
https://doi.org/10.1016/j.microrel.2014.01.005
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS).
A novel approach for estimating variation in the TDDB failure time is reported. The results for structures with Dual Damascene copper-based metallization and a low-k dielectric material demonstrate that variation in the initial current at stress reas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98af714b44ab7a503a45d5b675243e43
https://doi.org/10.1109/irps.2016.7574597
https://doi.org/10.1109/irps.2016.7574597