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pro vyhledávání: '"Cassé, M."'
Self-heating (SHE) TCAD numerical simulations have been performed, for the first time, on 30nm FDSOI MOS transistors at extremely low temperatures. The self-heating temperature rise dTmax and the thermal resistance Rth are computed as functions of th
Externí odkaz:
http://arxiv.org/abs/2309.04199
Autor:
Bédécarrats, T., Paz, B. Cardoso, Diaz, B. Martinez, Niebojewski, H., Bertrand1, B., Rambal, N., Comboroure, C., Sarrazin, A., Boulard, F., Guyez, E., Hartmann, J. -M., Morand, Y., Magalhaes-Lucas, A., Nowak, E., Catapano, E., Cassé, M., Urdampilleta, M., Niquet, Y. -M., Gaillard, F., De Franceschi, S., Meunier, T., Vinet, M.
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 1-4
Operating Si quantum dot (QD) arrays requires homogeneous and ultra-dense structures with aggressive gate pitch. Such a density is necessary to separately control the QDs chemical potential (i.e. charge occupation of each QD) from the exchange intera
Externí odkaz:
http://arxiv.org/abs/2304.03721
Autor:
Jacquinot, H., Maurand, R., Bada, G. Troncoso Fernandez, Bertrand, B., Cassé, M., Niquet, Y. M., de Franceschi, S., Meunier, T., Vinet, M.
In this paper, we report on simulations of an Electron Spin Resonance (ESR) RF control line for semiconductor electron spin qubits. The simulation includes both the ESR line characteristics (geometry and configuration, stack and material properties)
Externí odkaz:
http://arxiv.org/abs/2304.03705
Autor:
Bohuslavskyi, H., Barraud, S., Cassé, M., Barral, V., Bertrand, B., Hutin, L., Arnaud, F., Galy, P., Sanquer, M., De Franceschi, S., Vinet, M.
Publikováno v:
2017 Silicon Nanoelectronics Workshop (SNW), Kyoto, 2017, pp. 143-144
This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic ope
Externí odkaz:
http://arxiv.org/abs/2002.07070
Autor:
Bohuslavskyi, H., Barraud, S., Barral, V., Cassé, M., Guevel, L. Le, Hutin, L., Bertrand, B., Crippa, A., Jehl, X., Pillonnet, G., Jansen, A. G. M., Arnaud, F., Galy, P., Maurand, R., De Franceschi, S., Sanquer, M., Vinet, M.
Publikováno v:
IEEE Transactions on Electron Devices ( Volume: 65 , Issue: 9 , Sept. 2018 )
Extensive electrical characterization of ring oscillators (ROs) made in high-$\kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($\tau_
Externí odkaz:
http://arxiv.org/abs/1903.06021
Autor:
Bohuslavskyi, H., Jansen, A. G. M., Barraud, S., Barral, V., Cassé, M., Guevel, L. Le, Jehl, X., Hutin, L., Bertrand, B., Billiot, G., Pillonnet, G., Arnaud, F., Galy, P., De Franceschi, S., Vinet, M., Sanquer, M.
Publikováno v:
IEEE Electron Device Letters, 5 March 2019
In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) =
Externí odkaz:
http://arxiv.org/abs/1903.05409
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Publikováno v:
In Solid State Electronics December 2022 198
Autor:
Catapano, E., Cassé, M., Gaillard, F., de Franceschi, S., Meunier, T., Vinet, M., Ghibaudo, G.
Publikováno v:
In Solid State Electronics August 2022 194
Autor:
Catapano, E., Aprà, A., Cassé, M., Gaillard, F., de Franceschi, S., Meunier, T., Vinet, M., Ghibaudo, G.
Publikováno v:
In Solid State Electronics July 2022 193