Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Carson Henrion"'
Autor:
Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry Fair, David Johnson, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim H Jackson
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8a9dcf536e43c11c1edeba56d3412d1
https://doi.org/10.1109/isscc42615.2023.10067540
https://doi.org/10.1109/isscc42615.2023.10067540
Autor:
Thomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fdfc0b78f91b10db1be6ec0fb7a40fe
https://doi.org/10.1109/isscc42614.2022.9731678
https://doi.org/10.1109/isscc42614.2022.9731678
Autor:
Deepesh John, Amy Novak, Miguel Rodriguez, Alex Schaefer, Russell Schreiber, Stephen V. Kosonocky, Teja Singh, Sundar Rangarajan, Samuel D. Naffziger, Carson Henrion
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:102-114
AMD’s next-generation, high-performance, energy-efficient $\times 86$ core, Zen, targets server, desktop, and mobile client applications with a 52% instructions per clock cycle (IPC) uplift over the previous generation. The increase in IPC compleme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::125623032a8a3eeb77545f7a637b0c74
https://doi.org/10.1109/jssc.2017.2752839
https://doi.org/10.1109/jssc.2017.2752839
Autor:
Robert S. Orefice, Kevin Gillespie, Harry R. Fair, Stephen V. Kosonocky, Donald A. Priore, Samuel D. Naffziger, Sanjay Pant, Kathryn Wilcox, Ravinder Rachala, Jonathan White, Robert Cole, Benjamin Munger, Carson Henrion, Aaron Grenat, Ravi Jotwani
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:24-34
This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both integral pieces of the AMD Kaveri APU SoC which was implemented using a 28 nm high-K metal gate Bulk CMOS process. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75c49bdec1a85ea319a6842db8dc6961
https://doi.org/10.1109/jssc.2014.2357428
https://doi.org/10.1109/jssc.2014.2357428
Autor:
Joshua A. Bell, Teja Singh, Stephen V. Kosonocky, Sundar Rangarajan, Shane Southard, Carson Henrion, Hugh McIntyre, Ravi Jotwani, Edward Chang, Amy Novak, Alex Schaefer, Deepesh John, Michael Co
Publikováno v:
ISSCC
Codenamed “Zen”, AMD's next-generation, high-performance ×86 core targets server, desktop, and mobile client applications. Utilizing Global Foundries' energy-efficient 14nm LPP FinFET process, the 44mm2 Zen core complex unit (CCX) has 1.4B trans
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1531050832f06532f78b6846da5e7c8
https://doi.org/10.1109/isscc.2017.7870256
https://doi.org/10.1109/isscc.2017.7870256
Autor:
Kathryn Wilcox, Robert S. Orefice, Donald A. Priore, Stephen V. Kosonocky, Ravi Jotwani, Carson Henrion, Kevin Gillespie, Harry R. Fair, Jonathan White
Publikováno v:
ISSCC
The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal gate (HKMG) bulk CMOS using 12 levels of metal. It is designed to operate from 0.8 to 1.45V. The CPU module occupies 2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e41971aa6fe5cd36aac035029198b962
https://doi.org/10.1109/isscc.2014.6757357
https://doi.org/10.1109/isscc.2014.6757357
Autor:
Anita Karegar, Carson Henrion, Michael Dreesen, Michael K. Ciraula, Don R. Weiss, Russell Schreiber, John J. Wuu, Christopher George Helt, Ryan Freese, Bryan Schneller, Tommy Miles
Publikováno v:
ISSCC
High-performance multi-core processors require efficient multi-level cache hierarchies to meet high-bandwidth data requirements. Because level-3 (L3) cache is typically the largest cache on the die, the drive to lower cost places pressure on density,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a80f2408ca1589b48fb160e7e00c50ea
https://doi.org/10.1109/isscc.2011.5746309
https://doi.org/10.1109/isscc.2011.5746309