Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Carroll C. Speir"'
Autor:
Carroll C. Speir, Gabriele Manganaro, Jeffery Bray, Phil Brown, Qicheng Yu, Lawrence A. Singer, Donald Paterson, Tao Pan, Jeffrey Gealow, Siddharth Devarajan, Jose Barreiro Silva, Daniel F. Kelly, Frank Murden, Nevena Rakuljic, Todd Weigandt, Corey Petersen, Janet Brunsilius, Eric Otte, Daniel Rey-Losada
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:3204-3218
A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input sign
Publikováno v:
ISCAS
A new approach to linearize the cascade combination of multiple RF/mixed signal ICs, correcting in-situ for PCB imperfections and mutual loading is proposed. This allows to substantially reduce system design/prototyping cycles and to maximize the sig
Autor:
Nevena Rakuljic, Todd Weigandt, Corey Petersen, Eric Otte, Daniel Rey-Losada, Donald Paterson, Frank Murden, Tao Pan, Jose Barreiro Silva, Jeff Bray, Steve Kosic, Phil Brown, Lawrence A. Singer, Jeffrey Gealow, Janet Brunsilius, Qicheng Yu, Siddharth Devarajan, Daniel F. Kelly, Carroll C. Speir
Publikováno v:
ISSCC
Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The
Autor:
Jeff Bray, D Lattimore, R. Sneed, Scott Gregory Bardsley, G. Patterson, Andrew Stacy Morgan, R. Stop, M. Hensley, Ahmed Mohamed Abdelatty Ali, Scott Puckett, Christopher Daniel Dillon, Carroll C. Speir, Paritosh Bhoraskar, Huseyin Dinc
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:2602-2612
This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the
Autor:
Ahmed Mohamed Abdelatty Ali, Paritosh Bhoraskar, Peter Derounian, Carroll C. Speir, Bryce Gray, Matt McShea, Scott Puckett, Brad P. Jeffries, Ho-Young Lee, Jonathan Lanford, Ushma Mehta, Christopher Daniel Dillon, David Jarman, Huseyin Dinc, Janet Brunsilius
Publikováno v:
ISSCC
We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration signal to break th
Autor:
Carroll C. Speir, Robert Sneed, Paritosh Bhoraskar, M. Hensley, David Lattimore, Scott Puckett, Christopher Daniel Dillon, Greg Patterson, Scott Gregory Bardsley, Andrew Stacy Morgan, Russell Stop, Jeff Bray, Ahmed Mohamed Abdelatty Ali
Publikováno v:
ISSCC
Wireless communication applications have driven the development of high-resolution A/D converters (ADCs) with high sample rates, good AC performance and IF sampling capability to enable wider cellular coverage, more carriers, and to simplify the syst
Autor:
D. Kelly, K. Behel, M. Hensley, Michael R. Elliott, R. Stop, Scott Puckett, Frank Murden, M. Manglani, G. Patterson, Carroll C. Speir, J. Young, Carl W. Moreland
Publikováno v:
CICC
An integrated circuit is presented which receives an input IF frequency in the range of 70-300 MHz, and achieves 117 dB of dynamic range in a 200 kHz bandwidth (BW). An automatic-gain-control (AGC) loop is placed around the analog-to-digital converte