Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Carol Boye"'
Autor:
Carol Boye, DukKyun Moon, Steven McDermott, Norbert Arnold, Nicole Saulnier, Felix Levitov, Sam Choi, Alex Goldenshtein, Uri Smolyan, Noam Amit, Injo Ok, Iqbal Saraf
Publikováno v:
2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Autor:
A. Gaul, Andrew M. Greene, T. Levin, Dallas Lea, Victor Chan, Samuel S. Choi, Carol Boye, S. Mattam, J. S. Strane, Sean Teehan, Dechao Guo, Gauri Karve, Marc A. Bergendahl, Brad Austin, Kangguo Cheng
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 32:393-399
We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out fro
Publikováno v:
2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
An exponential correlation is found to exist between the number of added defects on polished blanket wafers and the inverse of defect size for particulate CMP defects. Smaller surface defects are much more abundant and more difficult to remove. Pad s
Autor:
Sanjay Mehta, Scott DeVries, Carol Boye, Wei-Tsu Tseng, Chen Jim C, Mary-Claire Silvestre, Thamarai S. Devarajan, Fee Li Lie, Massud A. Aminpur
Publikováno v:
2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI application is presented. A few novel methodologies were introduced to identify the source of defectivity in various BEOL sectors, such as, patterning, b
Transmission Electron Microscopy Sample Preparation By Design Based Recipe Writing in a DBFIB Part 2
Autor:
Marc A. Bergendahl, M. Biedrzycki, J. Hager, K. Nguyen, M. Persala, J. Arjavac, Brad Austin, Carol Boye, S. Shaar, Mary Breton, Michael Rizzolo, John G. Gaudiello, Sean Teehan, Shravan Matham, B. Cilingiroglu, James J. Demarest
Publikováno v:
International Symposium for Testing and Failure Analysis.
Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a fa
Autor:
Marc A. Bergendahl, Carol Boye, Jay W. Strane, Gauri Karve, Dechao Guo, T. Levin, S. Mattam, Dallas Lea, Kangguo Cheng, S. Choi, A. Gaul, Sean Teehan, Andrew M. Greene, Brad Austin, Victor S. Chan
Publikováno v:
2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto.
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 26:482-487
This paper proposes that the non-visual defect rate for Litho layers is an indicator of the quality of the process up to and including Litho. “Non-visual” (NV) defects are those detected by optical defect inspection systems but not re-detected by
Autor:
Sumanth Kini, Andrew Stamper, Charu Tejwani, Sang Y. Chong, Carol Boye, Ralf Buengener, Roland Hahn, Bryan N. Rhoads, Sean D. Burns, Kourosh Nafisi, Colin J. Brodsky, S. Fan
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 24:165-172
PWC (Process Window Centering) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection
Autor:
Jeffrey C. Shearer, Philip J. Oldiges, Soon-Cheon Seo, Terry A. Spooner, Matthew E. Colburn, Ravikumar Ramachandran, V. Sardesai, Kang-ill Seo, Dinesh Gupta, Richard G. Southwick, Xiao Sun, S. Stieg, H. Cai, S. Kanakasabaphthy, Vamsi Paruchuri, R. Sampson, Lars W. Liebmann, Walter Kleemeier, Kisik Choi, Deok-Hyung Lee, Christopher Prindle, R. Divakaruni, H. Shang, Abhijeet Paul, T. Gow, D. McHerron, Dechao Guo, Fee Li Lie, J. Nam, Neeraj Tripathi, Ruilong Xie, R. Kambhampati, Muthumanickam Sankarapandian, Balasubramanian S. Pranatharthi Haran, Carol Boye, James H. Stathis, B. Hamieh, John Iacoponi, Christopher J. Waskiewicz, Geum-Jong Bae, Derrick Liu, Sanjay Mehta, Reinaldo A. Vega, Terence B. Hook, Min Gyu Sung, Jay W. Strane, D.I. Bae, Robin Chao, Hoon Kim, F. Nelson, Theodorus E. Standaert, L. Jang, Erin Mclellan, M. Celik, S. Nam, Tae-Chan Kim, C.-C. Yeh, Sean D. Burns, P. Montanini, Charan V. V. S. Surisetty, Raghavasimhan Sreenivasan, Ju-Hwan Jung, B. Lherron, S.-B. Ko, E. Alptekin, Huiming Bu, Injo Ok, Jin Cho, Mukesh Khare, J. G. Hong, Gen Tsutsui, Andreas Scholze, Bomsoo Kim, D. Chanemougame, M. Mottura, M. Weybright, H. Mallela, K. Kim, Hemanth Jagannathan, Chanro Park, J. Jenq, Donald F. Canaperi, Young-Kwan Park, R. Jung, Kangguo Cheng
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A
Autor:
Scott Halle, Marcy Beard, Chiew-seng Koay, Oscar van der Straten, T. Levin, Lars Liemann, Juntao Li, D. Horak, Bryan Morris, Terry A. Spooner, S. Choi, Carol Boye, Donald F. Canaperi, Sylvie Mignot, Muthumanickam Sankarapandian, Elbert E. Huang, Chiahsun Tseng, James Hsueh-Chung Chen, Erin Mclellan, James J. Kelly, S. Fan, James J. Demarest, Nicole Saulnier, Hosadurga Shobha, Matthew E. Colburn, Balasubramanian S. Haran, Yongan Xu, Yunpeng Yin, Larry Clevenger, Christopher J. Waskiewicz, Mignot Yann, John C. Arnold
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) schem