Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Carlos Jesús Jiménez-Fernández"'
Autor:
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Antonio José Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Ricardo Chaves
Publikováno v:
Applied Sciences, Vol 12, Iss 5, p 2443 (2022)
The development of differential fault analysis (DFA) techniques and mechanisms to inject faults into cryptographic circuits brings with it the need to use protection mechanisms that guarantee the expected level of security. The AES cipher, as a stand
Externí odkaz:
https://doaj.org/article/bdbb4fab7ee54a7cb93ba99d13fae10e
Autor:
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutiérrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
Publikováno v:
Sensors, Vol 21, Iss 22, p 7596 (2021)
The security of cryptocircuits is determined not only for their mathematical formulation, but for their physical implementation. The so-called fault injection attacks, where an attacker inserts faults during the operation of the cipher to obtain a ma
Externí odkaz:
https://doaj.org/article/e53eb3b42e2d4c00a5b2d7d2234866e6
Autor:
Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena-Oliva, Pilar Parra-Fernández, Carlos Jesús Jiménez-Fernández
Publikováno v:
Sensors, Vol 20, Iss 23, p 6909 (2020)
One of the best methods to improve the security of cryptographic systems used to exchange sensitive information is to attack them to find their vulnerabilities and to strengthen them in subsequent designs. Trivium stream cipher is one of the lightwei
Externí odkaz:
https://doaj.org/article/bfc0af3908f44f2c9586ecd0d2476336
Autor:
F. Eugenio Potestad Ordonez, Carmen Baena Oliva, Manuel Valencia Barrero, Carlos Jesús Jiménez Fernández, Pilar Parra Fernandez
Publikováno v:
idUS. Depósito de Investigación de la Universidad de Sevilla
instname
instname
The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c855ac61e2465407dd8ceb2340090684
https://doi.org/10.1109/taee.2018.8476046
https://doi.org/10.1109/taee.2018.8476046
Autor:
Carmen Baena Oliva, Manuel Valencia Barrero, Carlos Jesús Jiménez Fernández, Pilar Parra Fernandez, F. Eugenio Potestad Ordonez
Publikováno v:
idUS. Depósito de Investigación de la Universidad de Sevilla
instname
instname
Digital design learning at the RT level requires practical examples and as learning progresses, the examples need to become more complex. FPGAs and development boards offer a very suitable platform for the implementation of these designs. However, cl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::65315c40097a0b0ba09bc674b93ed37d
Publikováno v:
Logic-Timing Simulation and the Degradation Delay Model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e4f888b78bce00520b18181bcbebe2c
https://doi.org/10.1142/9781860947360_0001
https://doi.org/10.1142/9781860947360_0001