Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Carlos A. Mazure"'
Autor:
Ivan Kasko, Manfred Moert, Walter Hartner, Marcus Kastner, Nicolas Nagel, Carlos A. Mazure, Thomas Mikolajick, Christine Dehm
Publikováno v:
Microelectronics Reliability. 41:947-950
Ferroelectric random access memories (FeRAMs) are new types of memories especially suitable for mobile applications due to their unique properties like nonvolatility, small DRAM-like cell size, fast read and write as well as low voltage/low power beh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bac0186d204b4bcc5b1152d3ffa9d41
https://doi.org/10.1016/s0026-2714(01)00049-x
https://doi.org/10.1016/s0026-2714(01)00049-x
Autor:
Zonimir Gabric, Carlos A. Mazure, Günther Schindler, Markus Kastner, Thomas Mikolajick, Christine Dehm, Peter Bosk, Gerhard Beitel, Walter Hartner
Publikováno v:
Integrated Ferroelectrics. 31:273-284
In this study, integration of an hydrogen barrier into a FeRAM process flow is investigated. It is reported in the literature that ferroelectric properties can be maintained after hydrogen annealing by using IrOx as a top electrode [16][17][18]. Adva
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9fb0fa2e4e5b9f55452ee6aaa1fa3cc
https://doi.org/10.1080/10584580008215660
https://doi.org/10.1080/10584580008215660
Degradation mechanisms of SrBi2Ta2O9 ferroelectric thin film capacitors during forming gas annealing
Autor:
Rainer Waser, Christine Dehm, Walter Hartner, Herbert Schroeder, Günther Schindler, Peter Bosk, Carlos A. Mazure
Publikováno v:
Integrated Ferroelectrics. 31:341-350
The effects of annealing in forming gas (5% hydrogen, 95% nitrogen; FGA) are studied on spin coated SrBi2Ta2O9 (SBT) thin films. SBT films on platinum bottom electrode are characterized with and without platinum top electrode by Scanning Electron Mic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b063afda121f9fd075fc97bcaf91b66e
https://doi.org/10.1080/10584580008215667
https://doi.org/10.1080/10584580008215667
Autor:
N. Junghans, P.-A. Weiß, Carlos A. Mazure, G. Schindler, Bernd O. Kolbesen, Christine Dehm, F Hintermaier, A Olbrich, S. A. Landau, Walter Hartner
Publikováno v:
Applied Surface Science. 157:387-392
Dielectric/ferroelectric materials such as BaxSr1−xTiO3 (BST), PbZrxTi1−xO3 (PZT), and SrBi2Ta2O9 (SBT) are currently being investigated for integration into high-density CMOS technology. In this study, the micromorphology of polycrystalline BST,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4c039b6760d60e5aca19595307b7255
https://doi.org/10.1016/s0169-4332(99)00555-3
https://doi.org/10.1016/s0169-4332(99)00555-3
Autor:
Barbara Hasler, Carlos A. Mazure, A. Gschwandtner, Christine Dehm, Werner Pamler, Volker Weinrich, E. Fritsch, U. Scheler, Nicolas Nagel, Thomas Röhr, H. Wendt, M. Engelhardt, Gerhard Beitel, R. Bergmann, Wolfgang Hönlein, K.-H. Malek
Publikováno v:
Microelectronic Engineering. 48:299-302
A new, low temperature (Ba,Sr)TiO 3 (BST) MOCVD process has been established at 580°C deposition temperature which can be used for Gbit DRAM applications using Ti TiN as barrier material. The process window for BST deposition was investigated in ter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc5cf06eaaf37d403e4d1f3547ac6f25
https://doi.org/10.1016/s0167-9317(99)00393-7
https://doi.org/10.1016/s0167-9317(99)00393-7
Autor:
Craig S. Lage, R.C. Taft, Craig D. Gunderson, P. Pelley, Bernard J. Roman, Jung-Hui Lin, K. Kemp, Arkalgud R. Sitaram, P.U. Kenkare, James D. Hayden, Carlos A. Mazure, Bich-Yen Nguyen, Ravi Subrahmanyan, Howard C. Kirsch, M. Woo, S. Radhakrishna
Publikováno v:
IEEE Transactions on Electron Devices. 41:2318-2325
An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddcf636456c4fd1389a32d629392f367
https://doi.org/10.1109/16.337444
https://doi.org/10.1109/16.337444
Autor:
Howard C. Kirsch, P. Crabtree, Sergio A. Ajuria, James D. Hayden, Carlos A. Mazure, J. Ko, James R. Pfiester, T. Vuong, Prashant Kenkare
Publikováno v:
IEEE Transactions on Electron Devices. 41:56-62
We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 /spl mu/m CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::492005b8e8b64fe4737a014d566e50a9
https://doi.org/10.1109/16.259620
https://doi.org/10.1109/16.259620
Autor:
Wayne J. Ray, Howard C. Kirsch, Scott S. Roth, C.D. Gunderson, K.J. Cooper, Carlos A. Mazure, J. Ko
Publikováno v:
IEEE Transactions on Electron Devices. 39:1085-1089
Device isolation has been most commonly achieved through the use of local oxidation of silicon (LOCOS) or LOCOS derivatives. LOCOS is a highly dependable, low-defect isolation technique, which explains its continued extensive use. Unfortunately, the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9550f7eea1d4bbae7a6d84f6c667920d
https://doi.org/10.1109/16.129087
https://doi.org/10.1109/16.129087
Publikováno v:
Microelectronic Engineering. 15:433-436
A new vertically layered elevated drain (VLED) structure is proposed, which is suitable, in terms of reliability and performance, for scaling down a MOSFET to the 0.25 ?m level without reducing the supply voltage below 3.3V. In this structure, a low
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73aa21bab694879932e1c9cf611af79a
https://doi.org/10.1016/0167-9317(91)90258-f
https://doi.org/10.1016/0167-9317(91)90258-f
Autor:
K. Barla, Carlos A. Mazure, Dean J. Denning, M. Haond, Craig D. Gunderson, B. Piot, Jon T. Fitch, A. Straboni
Publikováno v:
Microelectronic Engineering. 15:479-482
During selective epitaxial Si growth the wafers are exposed to a H 2 rich atmosphere. The impact of high temperature hydrogen prebake, typical of selective Si epitaxial processes, on thin dielectrics is investigated. A prebake temperature range of 85
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27593c3b8ecc4b60f45c3ac6181bc011
https://doi.org/10.1016/0167-9317(91)90268-i
https://doi.org/10.1016/0167-9317(91)90268-i