Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Carl Pixley"'
Autor:
Alfred Koelbl, Carl Pixley
Publikováno v:
International Journal of Parallel Programming. 33:645-666
Automating hardware design at higher levels of abstraction requires first and foremost a formal model of the high-level specification. This formal model is the basis of many EDA applications such as synthesis, analysis or verification. It should have
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e56bfb19e6df439065da5f364089db3
https://doi.org/10.1007/s10766-005-8910-3
https://doi.org/10.1007/s10766-005-8910-3
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 8:222-251
We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. Fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4310b7de259923ae6781e725ce75440
https://doi.org/10.1145/762488.762493
https://doi.org/10.1145/762488.762493
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20:249-265
We address the problem of developing suitable criteria for design replacement in the context of sequential logic synthesis. There have been previous efforts to characterize replacements for such designs. However, all previous attempts either make imp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee284308562091226c57a6c4d7d48e86
https://doi.org/10.1109/43.908455
https://doi.org/10.1109/43.908455
Publikováno v:
Journal of Electronic Testing. 16:107-120
Constraining and biasing are frequently used techniques to enhance the quality of randomized vector generation. In this paper, we present a novel method that combines constraints and input biasing in automatic bit-vector generation for block-level fu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac87fbe899e8550d5a16be7963cea7d5
https://doi.org/10.1023/a:1008301108750
https://doi.org/10.1023/a:1008301108750
Publikováno v:
Journal of Electronic Testing. 16:91-106
We present our formal combinational logic equivalence checking methods for industry-sized circuits. Our methods employ functional (OBDDs) algorithms for decisions on logic equivalence and structural (ATPG) algorithms to quickly identify inequivalence
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4157f4c22a40bef360d18ef42aaa8cdc
https://doi.org/10.1023/a:1008349024680
https://doi.org/10.1023/a:1008349024680
Autor:
Carl Pixley, Vigyan Singhal
Publikováno v:
International Journal on Software Tools for Technology Transfer (STTT). 2:288-306
Current practices in the verification of commercial hardware designs (digital, synchronous, and sequential semiconductors) are described. Recent advances in verification by the mathematical technique called model checking are described, and requireme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0580f350af27a5b4f6df26c554b24ce0
https://doi.org/10.1007/s100090050036
https://doi.org/10.1007/s100090050036
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:1024-1034
In order to reliably predict the behavior of a finite state machine (FSM) M or to generate acceptance tests for sequential designs, it is necessary to drive M to a predictable state or set of states. One possible way of accomplishing this is to have
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::059af65bf53befe43dcd52e6dd62cc81
https://doi.org/10.1109/43.298038
https://doi.org/10.1109/43.298038
Publikováno v:
Journal of Electronic Testing. 4:19-31
Asynchronizing sequence drives a circuit from an arbitrary power-up state into a unique state. Test generation on a circuit without a reset state can be much simplified if the circuit has a synchronizing sequence. In this article, a framework and alg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08a6a75846cae3904ec9c4ddeaf09090
https://doi.org/10.1007/bf00971937
https://doi.org/10.1007/bf00971937
Autor:
Carl Pixley
Publikováno v:
Hardware and Software: Verification and Testing ISBN: 9783642017018
Haifa Verification Conference
Haifa Verification Conference
We will discuss several years' experience with commercial HL-to-RTL equivalence checking with the Hector technology. We will also discuss several considerations based upon the reality that our company is an EDA vendor. This is quite different from th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e089700d68d95d231a47beefa5ef7ead
https://doi.org/10.1007/978-3-642-01702-5_6
https://doi.org/10.1007/978-3-642-01702-5_6
Publikováno v:
DAC
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence between ESL arrays and RTL memories can significantly reduce the complexity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2af5f4942f5a5fbc0fcd9e2cfbc1bc1a
https://doi.org/10.1109/dac.2007.375153
https://doi.org/10.1109/dac.2007.375153