Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Carl D. Dietz"'
Autor:
Carl D. Dietz, Tim Fischer, James Vinh, Samuel D. Naffziger, Kevin A. Hurd, Kathryn Wilcox, Dave Johnson, Jonathan White, Scott A. Hilker, Aaron Horiuchi, Srikanth Arekapudi, Golden Michael L, Hugh McIntyre, Eric W. Busta
Publikováno v:
ISSCC
AMD's 2-core “Bulldozer” module contains 213 million transistors in an 11-metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture [1] improves performance and frequency while reducing area a
Publikováno v:
COMPCON
Performance modeling was used in conjunction with application code traces to tune the PowerPC 603 microprocessor design. This modeling technique allowed the design space to be constrained by performance, power and size. Trade-offs were examined with
Autor:
J. Golab, K.R. Kishore, P. Voldstad, J. Slaton, D. Ogden, Mydung Pham, Christopher Hans Olson, Lee Evan Eisen, Russell Adley Reininger, J. Prado, Michael Clay Alexander, Y.-W. Ho, B. Burgess, P. Ippolito, Robert Thaddeus Golla, R. Harris, S.P. Litch, S.-H. Park, Soummya Mallick, M. Schiffli, Tai Ngo, C. Hunter, Belliappa Manavattira Kuttanna, B. Goins, Romesh Mangho Jessani, S. Reeve, Cang Tran, B. Ho, Carl D. Dietz, Arturo L. Arizpe, J. Eno, J. Kahle, S. Gary, K. Torku, H. Sanchez, R. El-Kareh, K. Hoover, G. Gerosa, D. Pham, G. Thuraisingham, Rajesh Bhikhubhai Patel, N. Vanderschaaf
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
This superscalar microprocessor is a 32b implementation of the PowerPC Architecture. With an estimated performance/power ratio of 25SPECint92/W at 80 MHz, this RISC style chip offers workstation-level performance packed into a low-power consumption,