A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

Autor: Laurent Millet, Lamine Benaissa, Caaliph Andriamisaina, Fabrice Guellec, Edith Beigne, Mehdi Darouich, Marc Duranton, Thomas Dombek, Edouard Deschaseaux, Karim Ben Chehida, Stéphane Chevobbe, Maria Lepecq

Publikováno v: IEEE Journal of Solid-State Circuits
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2019, 54 (4), pp.1096-1105. ⟨10.1109/JSSC.2018.2886325⟩
IEEE Journal of Solid-State Circuits, 2019, 54 (4), pp.1096-1105. ⟨10.1109/JSSC.2018.2886325⟩

This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integra

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7cfe9a69ea1285ac176103f138072b1e
https://hal-cea.archives-ouvertes.fr/cea-02186449

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Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques

Autor: Catherine Dezan, Alix Poungou, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Erwan Fabiani, Christophe Gouyen

Publikováno v: Techniques et sciences informatiques. 25:893-920

Reconfigurable architectures are similar. To ease their sof ware integration, the Madeo framework proposes a common model used by generic CAD t ools. The development of high level tools can rely on an open synthesis layer with be havioural and struct

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a109c4b065bbcc7641008ed65cae8208
https://doi.org/10.3166/tsi.25.893-920

Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit

Autor: Andriamisaina, Caaliph, Catherine, Dezan, Jego, Christophe, Bernard, Pottier

Publikováno v: ERSA'05

In this paper, an original method for the synthesis of one part of block turbo decoder is presented. From the abstract specifications, Madeo framework proposes an object oriented method to synthesize them onto FPGA structures. The method relies on th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::9a5f88887d8ec4c0cc5510525980a22c
https://hal.archives-ouvertes.fr/hal-00079265

High-Level Synthesis for Designing Multimode Architectures

Autor: Caaliph Andriamisaina, Cyrille Chavet, Emmanuel Casseau, Philippe Coussy

Publikováno v: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29 (11), pp.1736
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2010, 29 (11), pp.1736
HAL

This paper addresses the design of multimode architectures for digital signal and image processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c972f8b6df843fab5239636ab4bb6e96
https://hal.science/hal-00551454