Zobrazeno 1 - 10
of 1 344
pro vyhledávání: '"CPU multiplier"'
Autor:
Min-Seong Choo, Han-Gon Ko, Hankyu Chi, Sungwoo Kim, Deog-Kyoon Jeong, Soyeong Shin, Jinhyung Lee, Kwanseo Park, Sung-Yong Cho
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:2525-2538
Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work
Autor:
Dingxin Xu, Hanli Liu, Bangan Liu, Zheng Li, Kenichi Okada, Atsushi Shirane, Hongye Huang, Teruki Someya, Zheng Sun, Jian Pang
Publikováno v:
IEICE Transactions on Electronics. :289-299
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:298-309
This work presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based injection-locked clock multiplier (ILCM). Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the thr
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:3753-3763
This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circui
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:592-601
A ring oscillator (RO)-based low-noise frequency synthesizer is presented. Phase noise degradation caused by jitter accumulation in conventional RO-based synthesizers is alleviated by increasing the update rate. To this end, multiple phases of the cr
Publikováno v:
Analog Integrated Circuits and Signal Processing. 102:541-554
This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of d
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:2049-2058
A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL)
Autor:
Seojin Choi, Yongsun Lee, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi, Seyeon Yoo, Yongwoo Jo
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:927-936
An ultra-low-jitter, ring- LC -hybrid injection-locked clock multiplier (ILCM) is presented to achieve a high multiplication factor of 114. The proposed hybrid ILCM cascades a ring-type voltage-controlled oscillator (VCO)-based ILCM and an LC -type V
Autor:
Che-Wei Tien, Shen-Iuan Liu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 66:177-181
An injection-locked clock multiplier (ILCM) using a frequency calibrator is presented to tolerate the process, voltage, and temperature variations. By detecting the timing error between the delay cells of a voltage-controlled oscillator (VCO) with an
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:65-74
Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output freq