Zobrazeno 1 - 10
of 1 099
pro vyhledávání: '"CAS latency"'
Autor:
Michael Taylor, Dustin Richmond, Max Ruttenberg, Peitian Pan, Zhiru Zhang, Seyed Borna Ehsani, Preslav Ivanov, Krithik Ranjan, Dai Cheol Jung, Christopher Batten, Lin Cheng, Jack Weber, Bandhav Veluri, Zhongyuan Zhao
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:1620-1635
Future CPU-manycore heterogeneous systems can provide high peak throughput by integrating thousands of simple, independent, energy-efficient cores in a single die. However, there are two key challenges to translating this high peak throughput into im
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4065043b998b1326c9077db3d59bc0b2
https://doi.org/10.1109/tcad.2021.3103825
https://doi.org/10.1109/tcad.2021.3103825
Publikováno v:
Electronics, Vol 10, Iss 2291, p 2291 (2021)
Electronics
Volume 10
Issue 18
Electronics
Volume 10
Issue 18
The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f54807ea879becefde2ef4cf700ca5b5
Publikováno v:
IEEE Computer Architecture Letters. 20:90-93
Accurately modeling memory timing in a processor simulator is crucial for obtaining accurate and useful performance predictions. DRAM has a complex timing and reordering scheme, which results in highly varying access latencies depending on the type o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3044e222340c31e90eae54087eb60b4
https://doi.org/10.1109/lca.2021.3093075
https://doi.org/10.1109/lca.2021.3093075
Autor:
Lotfi Benmohamed, Frederic J. de Vaulx, Hakim Weatherspoon, Zhiming Shen, Christina Delimitrou, Charif Mahmoudi, Robbert van Renesse, Weijia Song
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 18:1-25
Infrastructure-as-a-Service cloud providers sell virtual machines that are only specified in terms of number of CPU cores, amount of memory, and I/O throughput. Performance-critical aspects such as cache sizes and memory latency are missing or report
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::409cb11cedc4c2fd3dc05506fa5ba0b5
https://doi.org/10.1145/3457373
https://doi.org/10.1145/3457373
Publikováno v:
Bioinformatics
Summary The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic da
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b8f4425d48f8ed9b151af927de115b61
https://doi.org/10.1093/bioinformatics/btab017
https://doi.org/10.1093/bioinformatics/btab017
Publikováno v:
IEEE Access, Vol 9, Pp 28930-28945 (2021)
RUC: Repositorio da Universidade da Coruña
Universidade da Coruña (UDC)
RUC. Repositorio da Universidade da Coruña
instname
RUC: Repositorio da Universidade da Coruña
Universidade da Coruña (UDC)
RUC. Repositorio da Universidade da Coruña
instname
[Abstract] Manycore processors feature a high number of general-purpose cores designed to work in a multithreaded fashion. Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Intel Mesh inte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b202ae3d3aa963e5f5fcf508e3517d0b
https://ieeexplore.ieee.org/document/9350627/
https://ieeexplore.ieee.org/document/9350627/
Publikováno v:
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 10:306-319
In state-of-the-art deep neural network (DNN), the layer-wise activation maps leads to significant data movement in hardware accelerators operating on real-time streaming inputs. We explore an architecture-aware algorithmic approach to reduce data mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c08919ad46c080094b0889eac5c36bb
https://doi.org/10.1109/jetcas.2020.3015889
https://doi.org/10.1109/jetcas.2020.3015889
Publikováno v:
Neural Networks. 128:142-149
Neural networks implemented with traditional hardware face inherent limitation of memory latency. Specifically, the processing units like GPUs, FPGAs, and customized ASICs, must wait for inputs to read from memory and outputs to write back. This moti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1106e5f87639d809d134a99e2a068f09
https://doi.org/10.1016/j.neunet.2020.04.025
https://doi.org/10.1016/j.neunet.2020.04.025
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 31:1255-1269
Many complex networks can be modeled as evolving graphs. Existing in-memory graph data structures are designed for DRAM. Thus, they cannot effectively exploit the current and ongoing adoption of emerging non-volatile main memory (NVMM) for two reason
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f47484add0c4cd21a91f6af98a8995d
https://doi.org/10.1109/tpds.2020.2965452
https://doi.org/10.1109/tpds.2020.2965452
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 17:1-26
In heterogeneous multicore systems, the memory subsystem plays a critical role, since most core-to-core communications are conducted through the main memory. Memory efficiency has a substantial impact on system performance. Although memory traffic fr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc2c6a282b69fea3d308709c9fb3379a
https://doi.org/10.1145/3377149
https://doi.org/10.1145/3377149