Zobrazeno 1 - 10
of 71
pro vyhledávání: '"C.K. Subramanian"'
Publikováno v:
Physica C: Superconductivity. 178:110-118
Preparation conditions for stabilizing the bulk superconductivity (T c=9.5 K ) in the nominal Bi 2 Sr 2 CuO ∼ 6 composition corresponding to the n=1 phase in the Bi 2 Sr 2 Ca n−1 Cu n O 2n+4 system are described. The samples Bi 2.1 Sr 1 .9 CuO y
Publikováno v:
Physical Review B. 43:6151-6154
Zero-field-cooled (ZFC) and field-cooled (FC) magnetization data for fields applied parallel and perpendicular to the plane of flat superconducting Pb discs (${\mathit{T}}_{\mathit{c}}$=7.2 K) are presented. A quasi-irreversibility temperature ${\mat
Publikováno v:
Solid State Communications. 76:175-179
We report the first measurement of contributions from multipole moments higher than the dipole of a non-uniformly magnetized intermediate state of a type I superconductor. In the specimen shape studied, these contributions are small compared to that
Publikováno v:
Proceedings of 1993 IEEE International SOI Conference.
Silicon-on-insulator (SOI) technology has surged into a position of prominence in recent years. SOI devices provide a viable technology for high-density, large-scale-integration and high performance VLSI circuits. Of late, the potential applications
Autor:
Y.-C. Ku, S.D. Hayden, K. Mocala, F J W Miller, M. Blackwell, C.K. Subramanian, W. Waldo, S. Ajuria, Matthew A. Thompson, J.R. Pfiester, B.M. James, B. Martino, H.-J. Lin
Publikováno v:
Proceedings of 1994 IEEE International Electron Devices Meeting.
A 0.25 /spl mu/m CMOS technology designed for a new symmetric Vss Cross-Under (XUnder) bitcell has been developed for a 64 Mb SRAM. The new symmetric bitcell is based on a simple geometry of orthogonal active and gate poly features which minimizes th
Autor:
C.K. Subramanian, G.W. Neudeck
Publikováno v:
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.
A novel single crystal silicon contacted double self-aligned transistor (DST) structure, that uses vertical seed epitaxial lateral overgrowth (VELO) is demonstrated. When scaled to smaller dimensions, this structure can provide an 18% improvement in
Autor:
G.W. Neudeck, C.K. Subramanian
Publikováno v:
1991 IEEE International SOI Conference Proceedings.
A SOI (silicon-on-insulator) process using ELO (epitaxial lateral overgrowth) is presented that can be used not only to create local area SOI islands but full wafer SOI as well. A thin full-wafer SOI structure formed with merged ELO has been demonstr
Autor:
C.K. Subramanian, Gerold W. Neudeck
Publikováno v:
Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium.
A full-wafer silicon-on-insulator (SOI) process using epitaxial lateral overgrowth is demonstrated. Merged selective epitaxial growth of silicon was used to create local area SOI islands. Chemical-mechanical polishing was used to form well-controlled
Publikováno v:
[Proceedings] 1990 IEEE 7th International Symposium on Applications of Ferroelectrics.
The time evolution of a phase grating was studied. The studies were carried out using pure LiNbO/sub 3/ and a Fe-doped samples. The formation and erasure times of the phase grating and the phase conjugate signal were measured using a 488-nm wavelengt
Autor:
John Damiano, H. Tian, M. Miscione, K. Cox, E. Deeters, C. Feng, M. Gibson, H. Nguyen, L. Zeng, M. Blackwell, C. Honcik, Y.-S. Feng, J. R. Zaman, J. Scott, J. Sebek, T. McNelly, James D. Hayden, C.K. Subramanian
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Summary form only given. Trench dislocations in a 0.25 /spl mu/m BiCMOS SRAM technology were traced to defects arising during S/D processing. It is argued that these defects coalesce to form dislocations, typically near the trench edge, under the com