Zobrazeno 1 - 10
of 38
pro vyhledávání: '"C.J.J. Dachs"'
Autor:
S. Nuttinck, E.A. Hijzen, C.J.J. Dachs, Andries J. Scholten, F. Cubaynes, C. Detcheverry, L.F. Tiemeijer
Publikováno v:
IEEE Transactions on Electron Devices. 53:153-157
For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with
Publikováno v:
IEEE Transactions on Electron Devices. 47:1507-1513
We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in de
Publikováno v:
Scopus-Elsevier
We present a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model contains Shockley-Read-Hall generation/recombination, trap-assisted tunneling, band-to-band-tunneling, and avalanche brea
Autor:
C.J.J. Dachs, Tom Schram, R. J. P. Lander, B. Kaczer, S. Biesemans, J.-L. Everaert, M. Demand, Zsolt Tokei, Werner Boullart, Johan Vertommen, Stephan Beckx, J.C. Hooker, Kirklen Henson, O. Richard, Hugo Bender, F. N. Cubaynes, B. Coenegrachts, M. Jurczak, W. Vandervorst, Monja Kaiser, Wim Deweerd
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/
Autor:
C.J.J. Dachs, Marc Schaekers, Aude Rothschild, Malgorzata Jurczak, Christopher S. Olsen, Robert O'Connor, Anabela Veloso, L. Date, Sofie Mertens, Robin Degraeve, F.N. Cubaynes
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
This paper investigates the use of pulsed-RF decoupled plasma nitridation (DPN) for the growth of oxynitride gate dielectrics for 65 nm general purpose (GP) applications. The effects of several DPN plasma parameters, base oxide thickness and post-nit
Autor:
Stefan Kubicek, Richard Lindsay, F.N. Cubaynes, C.J.J. Dachs, Z.M. Rittersma, J.C. Hooker, Josine Loo, Gerben Doornbos, Kirklen Henson, R. J. P. Lander, Youri Victorovitch Ponomarev, R. Surdeanu
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device
Autor:
Richard Lindsay, A. Satta, X. Pages, Radu Surdeanu, Kirklen Henson, C.J.J. Dachs, Bartek Pawlak, Anne Lauwers, Simone Severi, S. McCoy, J. Gelpey
Publikováno v:
Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials.
Autor:
A.C.M.C. van Brandenburg, Jurriaan Schmitz, W.M. Baks, P.A. Stolk, C.J.J. Dachs, S.F.M. Roes, Youri Victorovitch Ponomarev, Andreas H. Montree, H. Tuinhout
Publikováno v:
Scopus-Elsevier
Front-end optimization of a 0.15 /spl mu/m CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent
Autor:
Pierre H. Woerlee, P.A. Stolk, Andreas H. Montree, C.J.J. Dachs, Jurriaan Schmitz, R.F.M. Roes, Youri Victorovitch Ponomarev, A.C.M.C. van Brandenburg, Monja Kaiser
Publikováno v:
1999 Symposium on VLSI Technology: digest of technical papers : June 14-16, 1999, Kyoto, 65-66
STARTPAGE=65;ENDPAGE=66;TITLE=1999 Symposium on VLSI Technology
STARTPAGE=65;ENDPAGE=66;TITLE=1999 Symposium on VLSI Technology
We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this scheme, the Ge fraction in the poly-SiGe gate was used to
Autor:
Jeroen Croon, E. Augendre, F.R.J. Huisman, R.M.D.A. Velghe, K.N. Sreerambhatla, Youri Victorovitch Ponomarev, L.P. Bellefroid, M.N. Webster, M. Da Rold, E. Seevinck, Ray Duffy, M.J.B. Bolt, R.F.M. Roes, A.T.A. Zegers-van Duijnhoven, R. Surdeanu, M. Vertregt, Hans Tuinhout, A.J. Moonen, Peter Stolk, N.K.J. van Winkelhoff, C.J.J. Dachs
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimiza