Zobrazeno 1 - 10
of 28
pro vyhledávání: '"C.J. Zhai"'
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 4:523-529
Stress migration (SM) or stress-induced voiding experiments were conducted for two back-end-of-line (BEoL) technologies: Cu/FTEOS and Cu/low-k. Experiments have shown the mean time to failure (MTF) depends on inter-layer dielectric (ILD) materials pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1bad0d57fe11830163de732ba825bac
https://doi.org/10.1109/tdmr.2004.833225
https://doi.org/10.1109/tdmr.2004.833225
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 4:86-91
A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading condi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::810acfb0f05fa02cf2a52226e32f8497
https://doi.org/10.1109/tdmr.2003.822339
https://doi.org/10.1109/tdmr.2003.822339
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 3:207-212
Effects of ramp rate and dwell time are studied through laboratory results and a nts (DOE) using finite element analysis (FEA) incorporating stress/strain and plastic work history. Results demonstrate that solder joint fatigue life is more sensitive
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0734f97839345bb3725a8dff4502f3b5
https://doi.org/10.1109/tdmr.2003.820056
https://doi.org/10.1109/tdmr.2003.820056
Publikováno v:
2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.
In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and serv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64073106ba415023a50b5f9a398a37e1
https://doi.org/10.1109/itherm.2008.4544343
https://doi.org/10.1109/itherm.2008.4544343
Publikováno v:
2007 Proceedings 57th Electronic Components and Technology Conference.
Lid or heat spreader in flip chip packages has become a vital component for high performance and high power IC applications. While mechanics and reliability of flip chip packages have been extensively investigated in the last decade, majority of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb535c6cdce64794ce5dc1cb86c97634
https://doi.org/10.1109/ectc.2007.373933
https://doi.org/10.1109/ectc.2007.373933
Publikováno v:
56th Electronic Components and Technology Conference 2006.
Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL technology. To study the dependence of Cu/low-k delamination on package underf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7a1aeb7e3420de15532366898d0c85d
https://doi.org/10.1109/ectc.2006.1645735
https://doi.org/10.1109/ectc.2006.1645735
Publikováno v:
56th Electronic Components and Technology Conference 2006.
Underfill delamination jeopardy in flip chip organic packages is driven by shear and peeling interfacial stresses, which are directly impacted by underfill fillet geometry. Finite element analysis (FEA) models were used to analyze the effect of under
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0073d6d774e99af34c52e570880cddc
https://doi.org/10.1109/ectc.2006.1645871
https://doi.org/10.1109/ectc.2006.1645871
Design and process optimization for reliable resistor pack solder joints for microprocessor packages
Publikováno v:
2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).
The integration of several passives into a single component is essential to keep them in the vicinity of the microprocessor, and their reliability becomes critical for the overall robustness of the product. This paper uses both modeling and experimen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a2f7eeaba06c15c8c7e18add9c631141
https://doi.org/10.1109/ectc.2004.1319483
https://doi.org/10.1109/ectc.2004.1319483
Autor:
C.J. Zhai, Christine Hau-Riege, R.C. Blish, Amit P. Marathe, S. Taylor, H.W. Yao, Kurt Taylor, Darrell M. Erb, P.R. Besser
Publikováno v:
2004 IEEE International Reliability Physics Symposium. Proceedings.
Stress migration (SM) or stress-induced voiding (SIV) experiments were conducted for two BEoL (Back End of Line) technologies: Cu/FTEOS and Cu/Low-k. Experiments have shown the mean time to failure (MTF) depends on ILD (interlayer dielectric) materia
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a9f4128326b4beafa947d098cdc63aa
https://doi.org/10.1109/relphy.2004.1315329
https://doi.org/10.1109/relphy.2004.1315329
Publikováno v:
53rd Electronic Components and Technology Conference, 2003. Proceedings..
A generalized plane strain condition was assumed for an edge interfacial crack between die passivation and underfill for an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursion is applied as loadmg condit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c2edec1fa543546026b2e7c7a390f71
https://doi.org/10.1109/ectc.2003.1216362
https://doi.org/10.1109/ectc.2003.1216362