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pro vyhledávání: '"C.J. Pilch"'
Autor:
Sanjay K. Banerjee, Ashwin H. Shah, C.J. Pilch, Gordon P. Pollack, Bao Tran, Pallab K. Chatterjee, R.H. Womack, J. Gallia, Hisashi Shichijo, M. Elahy, William F. Richardson, D. Bordelon, H.E. Davis, Satwinder Malhi, Chu-Ping Wang
Publikováno v:
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89b83baec23a5aeb2dd2ba315c456161
https://doi.org/10.1109/isscc.1986.1156951
https://doi.org/10.1109/isscc.1986.1156951
Autor:
Hisashi Shichijo, James D. Gallia, Gordon P. Pollack, Satwinder Malhi, B. Tran, R.H. Womack, D.M. Bordelon, H.E. Davis, M. Elahy, Sanjay K. Banerjee, Ashwin H. Shah, Chu-Ping Wang, William F. Richardson, Pallab K. Chatterjee, C.J. Pilch
Publikováno v:
IEEE Journal of Solid-State Circuits. 21:618-626
An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2907e4d5d4aff3458fa16aedf52eae1b
https://doi.org/10.1109/jssc.1986.1052586
https://doi.org/10.1109/jssc.1986.1052586
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