Zobrazeno 1 - 10
of 91
pro vyhledávání: '"C.-I.H. Chen"'
Publikováno v:
IEEE Transactions on Microwave Theory and Techniques. 45:2283-2295
A design for the monobit-receiver application-specific integrated circuit (ASIC) will be described. The monobit receiver is a wide-band (1-GHz) digital receiver designed for electronic-warfare applications. The receiver can process two simultaneous s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fe900dff2ce8c9af5d0d408b3ab8a8a
https://doi.org/10.1109/22.643832
https://doi.org/10.1109/22.643832
Autor:
J.T. Yuen, C.-I.H. Chen
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2:273-291
Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18e393e390c25fd42421ba57a685d4b2
https://doi.org/10.1109/92.311637
https://doi.org/10.1109/92.311637
Autor:
C.-I.H. Chen, M. Wagh
Publikováno v:
ISCAS (6)
Current synthesis tools are capable of handling area and timing constraints. Synthesis for testability process ensures that the design is testable. In this paper CAD tools capable of handling the testability requirements are explained and emphasis is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24bc6d5d75246c157b9448091d5454ba
https://doi.org/10.1109/iscas.1999.780169
https://doi.org/10.1109/iscas.1999.780169
Autor:
M. Wagh, C.-I.H. Chen
Publikováno v:
Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).
Synthesis for testability process ensures that the design is testable, which exploits the fundamental relationships between don't care and redundancy in combinational and sequential circuits. In this paper a testability synthesis with redundancy remo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ee2b7367988fd2161250f6b4447c9f9
https://doi.org/10.1109/asic.1999.806490
https://doi.org/10.1109/asic.1999.806490
Autor:
C.-I.H. Chen, G.E. Sobelman
Publikováno v:
ICCD
In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d50446a7d7ee4e1776f6dcf5072fbab
https://doi.org/10.1109/iccd.1989.63431
https://doi.org/10.1109/iccd.1989.63431
Publikováno v:
ICCD
A network partitioning tool, named Autonomous, is presented for partitioning digital combinational portions of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. A built-in self-test (BIST) de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::082f30723f2596e98190953ac986e352
https://doi.org/10.1109/iccd.1992.276265
https://doi.org/10.1109/iccd.1992.276265
Autor:
C.-I.H. Chen
Publikováno v:
ICCD
At present, there is no efficient synthesis approach for multiport memory synthesis in data path design and only single port memory is considered for register allocation in most synthesis systems. An efficient method, partitioned dependence matrix (P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec2071e2440ebc023e80b0a3076d4b4d
https://doi.org/10.1109/iccd.1991.139934
https://doi.org/10.1109/iccd.1991.139934
Autor:
C.-I.H. Chen, R. Smith
Publikováno v:
IEEE International Conference on Systems Engineering.
Techniques for built-in self-test (BIST) are examined. They can be used to modify an existing systolic array controller chip and a multiplier/accumulator chip, called a systolic array cell, so that self-testing can be performed. The goal is to implem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d19720da9b947f803cbe5b528f59a070
https://doi.org/10.1109/icsyse.1990.203142
https://doi.org/10.1109/icsyse.1990.203142
Autor:
C.-I.H. Chen, Xin Yuan
Publikováno v:
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).
Given a set of pre-computed test vectors obtained by an automatic test pattern generation (ATPG) tool for detecting random-pattern-resistant faults or particular hard-to-test faults presented in a circuit under test (CUT), a simple test generator bas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d753b7605ffd1fca13b59c4e8441168a
https://doi.org/10.1109/asic.1998.722807
https://doi.org/10.1109/asic.1998.722807
Publikováno v:
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).
A design for the monobit receiver application specific integrated circuit (ASIC) is described. The monobit receiver is a wide band (1 GHz) digital receiver designed for electronic warfare applications. The receiver can process two simultaneous signal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0b6a6164ab702e4724034a4ad7fc645
https://doi.org/10.1109/asic.1997.616994
https://doi.org/10.1109/asic.1997.616994