Zobrazeno 1 - 10
of 32
pro vyhledávání: '"C. Tirumurti"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:238-246
The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a878c4c457833f116c92764d3f9be123
https://doi.org/10.1109/tvlsi.2016.2572606
https://doi.org/10.1109/tvlsi.2016.2572606
Publikováno v:
Journal of Electronic Testing. 29:351-366
Modern microprocessors incorporate a variety of architectural features, such as branch prediction and speculative execution, which are not critical to the correctness of their operation yet are essential towards improving performance. Accordingly, wh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c834c33fe88ea6324f5cc227fb86fc4
https://doi.org/10.1007/s10836-013-5360-5
https://doi.org/10.1007/s10836-013-5360-5
Publikováno v:
DFT
The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0e2bc95d0df16ffe288a2efdc14fb69a
https://doi.org/10.1109/dft.2014.6962063
https://doi.org/10.1109/dft.2014.6962063
During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::12d7f9c9d631abdf44cb275a1ffb9c17
http://hdl.handle.net/11568/1025936
http://hdl.handle.net/11568/1025936
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1890-1894
We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illino
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92bed27486268e3105deb4e6020905d2
https://doi.org/10.1109/tvlsi.2011.2163651
https://doi.org/10.1109/tvlsi.2011.2163651
Publikováno v:
IEEE Transactions on Computers. 61:1361-1370
Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation. In order to effectively allocate design for reliability resources, GSV analys
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ca16939a8dd527291dfd78cf3746bc2
https://doi.org/10.1109/tc.2011.172
https://doi.org/10.1109/tc.2011.172
Publikováno v:
IEEE Transactions on Computers. 60:1260-1273
We investigate the correlation between low-level faults in the control logic of a modern microprocessor and their instruction-level impact on the execution of typical workload. Such information can prove immensely useful in accurately assessing and p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::504573a1cbabba3a06ec7200de39f051
https://doi.org/10.1109/tc.2010.60
https://doi.org/10.1109/tc.2010.60
Publikováno v:
IEEE Transactions on Computers. 60:1274-1287
We present a Concurrent Error Detection (CED) scheme for the Scheduler of a modern microprocessor. The proposed CED scheme is based on monitoring a set of invariances imposed through added hardware, violation of which signifies the occurrence of an e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fb4c094c693b3fe0a663c256221f76f
https://doi.org/10.1109/tc.2010.265
https://doi.org/10.1109/tc.2010.265
Publikováno v:
ETS
Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e965289037c766c3de57f2f5f80a528c
https://doi.org/10.1109/ets.2013.6569375
https://doi.org/10.1109/ets.2013.6569375
Publikováno v:
DFT
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction executing in the processor. To evaluate the proposed method, we use a s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7d3f17a8a327022a0ac339c087902ea
https://doi.org/10.1109/dft.2008.59
https://doi.org/10.1109/dft.2008.59