Zobrazeno 1 - 10
of 10
pro vyhledávání: '"C. Senthilpar"'
Publikováno v:
Scientific Reports, Vol 12, Iss 1, Pp 1-18 (2022)
Abstract In wireless communication networks, the necessity for high-speed data rates has increased in emerging 5G application areas. The Power Amplifier (PA) topologies reported to date achieved desired Power Added Efficiency (PAE) and linearity. How
Externí odkaz:
https://doaj.org/article/149d0e7666134c988f6b643dceda78a0
Publikováno v:
International Journal of Electronics and Telecommunications, Vol vol. 65, Iss No 3, Pp 477-483 (2019)
This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full ad
Externí odkaz:
https://doaj.org/article/2dce13c1c4db4829a85e4fe948e62c72
Publikováno v:
Journal of Engineering Science and Technology, Vol 13, Iss 6, Pp 1636-1650 (2018)
The new trend of the DRAM design is to characterize by its reliability, delay, low power dissipation, and area. This paper dealt with the design of 1-bit DRAM and efficient implementation of a sense amplifier. The proposed 1-bit DRAM designed using d
Externí odkaz:
https://doaj.org/article/a07d54005daa4a408006f5dd12809c7a
Publikováno v:
Journal of Engineering Science and Technology, Vol 13, Iss 3, Pp 822-837 (2018)
The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor lo
Externí odkaz:
https://doaj.org/article/10eb410592ef4719a362d7dfe4fc39a4
Publikováno v:
Engineering Science and Technology, an International Journal, Vol 20, Iss 1, Pp 35-40 (2017)
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout g
Externí odkaz:
https://doaj.org/article/abb2c1e49e6c4fb8b50d5940b7386ef0
Publikováno v:
Journal of Engineering Science and Technology, Vol 9, Iss 2, Pp 167-175 (2014)
This paper mainly focuses on pass logic based design, which gives an low Energy Per Instruction (EPI) and high throughput COrdinate Rotation Digital Computer (CORDIC) cell for application of robotic exploration. The basic components of CORDIC cell na
Externí odkaz:
https://doaj.org/article/1ba0dc1000044b9a85ca2808126a1d03
Publikováno v:
Journal of Engineering Science and Technology, Vol 8, Iss 6, Pp 764-777 (2013)
This paper presents a novel high-speed and high-performance multiplexer based full adder cell for low-power applications. The proposed full adder is composed of two separate modules with identical hardware configurations that generate Sum and Carry s
Externí odkaz:
https://doaj.org/article/9b2ca913a73d4ffaa1322d6478eb5fa5
Publikováno v:
Asian Journal of Scientific Research. 9:1-12
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6154f405083aa4bd3bcc3abdc7079fc9
https://doi.org/10.3923/ajsr.2016.1.12
https://doi.org/10.3923/ajsr.2016.1.12
Publikováno v:
Asian Journal of Scientific Research. 8:381-391
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7af7b41924353244452c17ddb60bec5e
https://doi.org/10.3923/ajsr.2015.381.391
https://doi.org/10.3923/ajsr.2015.381.391
Publikováno v:
Asian Journal of Scientific Research. 6:666-678
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3434d715d889c8e2375b1ee5a82887a8
https://doi.org/10.3923/ajsr.2013.666.678
https://doi.org/10.3923/ajsr.2013.666.678