Zobrazeno 1 - 10
of 37
pro vyhledávání: '"C. Pelto"'
Autor:
A. Elsherbini, K. Jun, S. Liff, T. Talukdar, J. Bielefeld, W. Li, R. Vreeland, H. Niazi, B. Rawlings, T. Ajayi, N. Tsunoda, T. Hoff, C. Woods, G. Pasdast, S. Tiagaraj, E. Kabir, Y. Shi, W. Brezinski, R. Jordan, J. Ng, X. Brun, B. Krisnatreya, P. Liu, B. Zhang, Z. Qian, M. Goel, J. Swan, G. Yin, C. Pelto, J. Torres, P. Fischer
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Autor:
Yeoh Andrew W, W. Han, Manvi Sharma, J. Shin, I. Post, M. Tanniru, T. Mule, Madhavan Atul, Gerald S. Leatherman, Kevin J. Fischer, Y-H. Wu, M. Sprinkle, Prasun Sinha, S. Anand, J. Steigerwald, S. Nigam, V. Souw, C. Ganpule, M. Asoro, Haran Mohit K, K-S. Lee, C. Pelto, P. Yashar, S. Samarajeewa, M. Mori, A. Tripathi, S. Kirby, C. Auth, M. Aykol, H. Hiramatsu, K. Marla, H. Jeedigunta, V. Chikarmane, M. Buehler, Nicholas J. Kybert
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduce
Autor:
V. Chikarmane, M. Hattendorf, S. Kosaraju, Abdur Rahman, M. Sprinkle, A. Tura, V. Sharma, G. Leatherman, H. Gomez, G. Ding, D. Towner, P. Sinha, C. Auth, S. Jaloviar, J. Birdsall, I. Post, B. Ho, D. Bergstrom, J. Leib, K. Lee, T. Mule, D. Hanken, M. Asoro, A. Saha, M. Sharma, C. Pelto, H. Meyer, M. Prince, L. Pipes, C. Staus, J. Shin, R. Heussner, S. Parthasarathy, C. Parker, V. Bhagwat, C. Ward, J. Dacuna Santos, M. Buehler, H. Hiramatsu, R. Suri, A. Aliyarukunju, M. Haran, S. Rajamani, A. Tripathi, P. Smith, A. Madhavan, W. Han, A. Yeoh, N. Bisnik, K. Marla, S. Joshi, H. Kothari, Q. Fu, I. Jin, S. Kirby, A. St. Amour
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-al
Autor:
Patel Reken, P. Yashar, C. Pelto, I. Tsameret, C. Petersburg, J. Longun, I. Jin, D. Ingerly, L. Rockford, Hsiao-Kang Chang, Conor P. Puls, P. Plekhanov, Muhammet Uncuer, Kevin J. Fischer, H. Kilambi
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
We describe here performance enhancement to Intel's 14nm high-performance logic technology interconnects and back end stack and introduce the SOC technology family of interconnects. Enhancement includes improved RC performance and intrinsic capacitan
Autor:
Patel Reken, P. Plekhanov, S. Rajamani, P. Reese, Conor P. Puls, Muhammet Uncuer, Rahim Kasim, E. Hwang, M. Agostinelli, M. Bost, Swaminathan Sivakumar, S. Nigam, Sanjay Natarajan, P. Charvat, S. Kosaraju, M. Prince, D. Rao, B. Song, M. Yang, S. Williams, P. Yashar, K. S. Lee, Pulkit Jain, I. Jin, Q. Fu, H. Hiramatsu, Kevin J. Fischer, Max M. Heckscher, R. McFadden, V. Chikarmane, Haran Mohit K, A. Rosenbaum, Huichu Liu, D. Bahr, C. Ganpule, C. Pelto, C. Allen
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple
Autor:
K. Fischer, Pulkit Jain, Sell Bernhard, P. Plekhanov, Swaminathan Sivakumar, S. Rajamani, R. James, Mark Y. Liu, C. Kenyon, L. Neiberg, Pete Smith, J. Wiedemer, M. Haran, M. Prince, Kevin Zhang, A. Bowonder, S. Morarka, R. Mehandru, B. Song, M. Agostinelli, Q. Fu, Y. Luo, W. Han, M. Heckscher, R. Grover, R. Patel, V. Chikarmane, S. Akbar, S. Chouksey, P. Patel, D. Hanken, I. Jin, L. Pipes, C. Parker, J. Sandford, M. Giles, Paul A. Packan, Tahir Ghani, A. Paliwal, E. Haralson, M. Bost, K. Tone, Sanjay Natarajan, M. Yang, Eric Karl, Hei Kam, R. Jhaveri, R. Heussner, T. Troeger, A. Dasgupta, S. Govindaraju, C. Pelto
Publikováno v:
2014 IEEE International Electron Devices Meeting.
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The
Publikováno v:
Acta Horticulturae. :119-124
Few studies with random amplified polymorphic DNA (RAPD) markers have focused on blackberry genotypes. In this study we attempted to differentiate several blackberry and raspberry cultivars for genetic identification by pedigree and RAPD analyses. Ru
Autor:
Matthew C. Pelto, Jon T. Lindstrom
Publikováno v:
Carnivorous Plant Newsletter. 32:74-77
Publikováno v:
Journal of Environmental Horticulture. 21:57-60
Randomly amplified polymorphic DNA (RAPD) markers were used to distinguish five remontant and two cold-hardy Hy- drangea macrophylla (Thunb.) Ser. taxa. Eleven primers generated sufficient polymorphisms to separate these seven culti- vars into two gr
Autor:
Matthew C. Pelto, Jon T. Lindstrom
Publikováno v:
Journal of Environmental Horticulture. 21:6-10
Itea virginica L., Virginia sweetspire, is a flowering shrub native to the eastern United States. It has become popular recently due to its multiple seasons of interest, ease of propagation, and relative lack of significant insect or disease problems