Zobrazeno 1 - 10
of 38
pro vyhledávání: '"C. Kampen"'
Publikováno v:
Solid-State Electronics. :114-122
The influence of rapid thermal annealing (RTA) and millisecond annealing (MSA) peak temperature fluctuations, due to pattern effects, on Schottky contact resistances and the electrical properties of 6-T SRAM cells is studied in this work. TCAD simula
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f51f65e53af6a931c3675072aac28884
https://doi.org/10.1016/j.sse.2011.06.005
https://doi.org/10.1016/j.sse.2011.06.005
Autor:
C. P. J. Salzig, R. Jancke, Siegfried Selberherr, Jurgen Lorenz, Peter Evanschitzky, C. Kampen, E. Bär, Tanja Clees, U. Paschen
Publikováno v:
IEEE Transactions on Electron Devices. 58:2227-2234
Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6de2be12501e4497f45c6840107d125c
https://doi.org/10.1109/ted.2011.2150226
https://doi.org/10.1109/ted.2011.2150226
Publikováno v:
Thin Solid Films. 518:2478-2484
Development and optimization of electronic devices in industrial and academic environments would hardly be conceivable without the numerical simulation of their processing and electronic behavior. In the past, model development efforts aimed especial
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fff0d4c3ac6b945e3f43c45073465a49
https://doi.org/10.1016/j.tsf.2009.09.150
https://doi.org/10.1016/j.tsf.2009.09.150
Autor:
C. Kampen, Alexander Burenkov, Arnaud Bournel, V. Aubry-Fortuna, Heiner Ryssel, Jurgen Lorenz
Publikováno v:
IEEE Transactions on Electron Devices. 55:3227-3235
This paper presents a quantum-mechanical modification of the conventional drift-diffusion model for simulation of quasi-ballistic carrier transport under high-field conditions. Thereby, the saturation velocity of charge carriers has been adjusted in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::baa577d34f429b136a97053f4049b893
https://doi.org/10.1109/ted.2008.2004474
https://doi.org/10.1109/ted.2008.2004474
Publikováno v:
2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
In this paper we present an extensive comparison of tunneling device simulations versus experimental results. Different tunneling models were used to simulate long channel silicon on insulator tunneling field effect transistors. The results were comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd401dbf69aa90b340d0cf1fce0a7628
https://doi.org/10.1109/essderc.2011.6044215
https://doi.org/10.1109/essderc.2011.6044215
Publikováno v:
2010 Proceedings of the European Solid State Device Research Conference.
The influence of temperature variations during flash annealing on contact resistances in 6-T SRAM cells was studied. TCAD simulations of 32 nm single gate FD SOI devices were carried out. The active regions of a 6-T SRAM cell were simulated by 3D pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7d3935bce992f53475d7490d1014986
https://doi.org/10.1109/essderc.2010.5618359
https://doi.org/10.1109/essderc.2010.5618359
Publikováno v:
2010 International Conference on Simulation of Semiconductor Processes and Devices.
A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::031b1a6960747fe3d3d625ae806b9ef1
https://doi.org/10.1109/sispad.2010.5604543
https://doi.org/10.1109/sispad.2010.5604543
Publikováno v:
2009 International Symposium on VLSI Technology, Systems, and Applications.
Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e40c6f61879c261167af46f50757366e
https://doi.org/10.1109/vtsa.2009.5159272
https://doi.org/10.1109/vtsa.2009.5159272
Publikováno v:
2009 10th International Conference on Ultimate Integration of Silicon.
The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d52970d38e0088e68dffe35d5f0dcfa0
https://doi.org/10.1109/ulis.2009.4897589
https://doi.org/10.1109/ulis.2009.4897589
Publikováno v:
ESSDERC 2008 - 38th European Solid-State Device Research Conference.
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::851565aed5ba2932e76b8fe3f7cb7996
https://doi.org/10.1109/essderc.2008.4681731
https://doi.org/10.1109/essderc.2008.4681731