Výsledky vyhledávání - "C. Ferrandon"

A Versatile Platform towards High Reliability Compact Package for Digital Chips

Autor: L. Toffanin, J-P. Peltier, G. Simon, V. Puyal, B. Kholti, J-C. Souriau, C. Ferrandon, L. Castagne, G. Waltener, R. Lemaire, T. Lacrevaz

Publikováno v: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
2017 IEEE 67th Electronic Components and Technology Conference (ECTC), May 2017, Orlando, United States. pp.623-630, ⟨10.1109/ECTC.2017.331⟩

A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The elec

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2c192e968cd954cf953dca17d64c83db
https://hal.science/hal-02017756

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Warpage reduction using dielectric layers stress tuning: From analytical model to 3D integration of large die on ceramic substrate

Autor: G. Imbert, Laetitia Castagne, Gilles Simon, F. Casset, Pascal Chevalier, N. Chevrier, B. Kholti, L. Toffanin, Sébastien Petitdidier, F. Bailly, Jp. Pierrel, D. Mermin, R. Franiatte, C. Ferrandon

Publikováno v: 2016 6th Electronic System-Integration Technology Conference (ESTC).

A mechanical study of silicon interposer bow reduction, from wafer level manufacturing to large die stacking including analytical modeling, is presented in this paper. Indeed, understanding and reducing the warpage of a dissymmetrical substrate is fu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5850f68bc6ecd5229641ea5556d1a7a1
https://doi.org/10.1109/estc.2016.7764485

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Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach

Autor: C. Ferrandon, G. Simon, Y. Lamy, J.F. Carpentier, Sylvain Joblot

Publikováno v: International Symposium on Microelectronics. 2012:000233-000238

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3d6b584a5aebf924a8fdfb5cf869fcf8
https://doi.org/10.4071/isom-2012-tp11

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A compact 3D silicon interposer package with integrated antenna for 60GHz wireless applications

Autor: Alexandre Siligaris, Yann Lamy, C. Ferrandon, Cedric Dehos, O. El Bouayadi, Laurent Dussopt, P. Vincent

Publikováno v: 3DIC

A 6.5×6.5 mm2 compact silicon interposer encompassing 2 Tx/Rx antenna, one RF chips, TSV via-last has been designed and fabricated for 60 GHz fast data transmission applications. First characterizations are described in this paper with a focus on re

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::397ca9343d7af66dbbd4ea71e116f13b
https://doi.org/10.1109/3dic.2013.6702345

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Innovative wafer-level encapsulation & underfill material for silicon interposer application

Autor: A. Schreiner, Yann Lamy, Sylvain Joblot, Severine Cheramy, C. Ferrandon, Maxime Argoud, A. Jouve, P. Montmeat, Gilles Simon, M. Pellat, Frank Fournel

Publikováno v: 2013 IEEE 63rd Electronic Components and Technology Conference.

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “sil

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::feb729078d2579a7ed027165089a60bb
https://doi.org/10.1109/ectc.2013.6575658

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Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

Autor: J. Roullard, P. Leduc, Grégory Houzet, C. Ferrandon, Cedric Bermond, Thierry Lacrevaz, S. Capraro, Bernard Flechet, Jean Charbonnier, C. Fuchs, Alexis Farcy

Publikováno v: IEEE 62nd Electronic Components and Technology Conf.
IEEE 62nd Electronic Components and Technology Conf., May 2012, San Diego, United States

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::82df804e2de21f797eef916dc61e9cfc
https://doi.org/10.1109/ectc.2012.6248798

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