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pro vyhledávání: '"C. D'Ernic"'
Autor:
E.P. Gusev, V. Narayanan, S. Zafar, C. Cabral, E. Cartier, N. Bojarczuk, A. Callegari, R. Carruthers, M. Chudzik, C. D'Ernic, E. Duch, P. Jamison, P. Kozlowski, D. LaTulipe, K. Maitra, F.R. McFeely, J. Newbury, V. Paruchuri, M. Steen
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T/sub inv/, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::befd9fcbf8afd507f599086ce4a8a732
https://doi.org/10.1109/iedm.2004.1419274
https://doi.org/10.1109/iedm.2004.1419274
